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REJ09B0354-0400
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16
H8S/2355 Group
Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
H8S/2355 H8S/2353 H8S/2393
HD6432355 HD6472355 HD6432353 HD6432393
Rev.4.00 Revision date: Feb. 13, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
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General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.
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Preface
The H8S/2355 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT * ) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer 2 (WDT), serial communication interface (SCI), A/D converter, D/A converter* , and I/O ports. An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2355 Group enables compact, high-performance systems to be implemented easily. This manual describes the hardware of the H8S/2355 Group. Refer to the H8S/2600 Series and H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes: *1 ZTAT is a registered trademark of Renesas Technolgy Corp. There is no PROM version of the H8S/2393. *2 The H8S/2393 does not support a D/A converter.
(R)1
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Main Revisions for This Edition
Item All Page -- Revision (See Manual for Details) * * 1.3.3 Pin Functions Table 1.3 Pin Functions 18 Notification of change in company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Product naming convention amended (Before) H8S/2355 Series (After) H8S/2355 Group
Pin No. Type Bus control Symbol CS7 to CS0 TFP-120 FP-128 I/O Name and Function
Table 1.3 amended
29, 30, 33, 34, Output Chip select: Signals for selecting 61, 60, 69, 66, areas 7 to 0. 117 to 120 127, 128, 1, 2 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space.
AS
RD
83
91
HWR
84
92
LWR
85
93
WAIT
86
94
2.6.3 Table of Instructions Classified by Function Table 2.3 Data Transfer Instructions 3.3.5 Mode5
49
Table 2.3 amended C [( of )] C
76
Description amended ... an address bus, port D functions as a data bus, ...
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Item 3.4 Pin Functions in Each Operating Mode Table 3.3 Pin Functions in Each Mode
Page 77
Revision (See Manual for Details) Table 3.3 amended
Port Port A PA7 to PA5 PA4 to PA0 Port B Port C Port D Port E A A D P*/D P*/A P*/A D P*/D P P P P Mode 1 P Mode 2 P Mode 3 P Mode 4 P*/A A A A D P/D*
3.5 Memory Map in Each Operating Mode Figure 3.1 Memory Map in Each Operating Mode in the H8S/2355
78
Figure 3.1 amended
Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000
On-chip ROM
H'DFFF H'E000 External address space H'EC00 On-chip RAM*
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Item 3.5 Memory Map in Each Operating Mode Figure 3.1 Memory Map in Each Operating Mode in the H8S/2355 (cont)
Page 79
Revision (See Manual for Details)
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
H'00FFFF H'010000 On-chip ROM/ external address space*1
H'00FFFF H'010000 On-chip ROM/ reserved area*2
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3
H'01FFFF
H'FFEC00 On-chip RAM H'FFFBFF
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Item 3.5 Memory Map in Each Operating Mode Figure 3.2 Memory Map in Each Operating Mode in the H8S/2353
Page 80
Revision (See Manual for Details) Figure 3.2 amended
Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000
On-chip ROM
H'DFFF H'E000 External address space H'EC00 Reserved area H'F400
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Item 3.5 Memory Map in Each Operating Mode Figure 3.2 Memory Map in Each Operating Mode in the H8S/2353 (cont)
Page 81
Revision (See Manual for Details)
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
On-chip ROM
H'00FFFF H'010000 External address space/reserved area*1
H'020000 H'FFEC00
External address space Reserved area
5.6.2 Block Diagram Figure 5.9 Interrupt Control for DTC 6.3.2 Bus Specifications 6.4.5 Wait Control
123
Figure title amended
141
Description amended (1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area ...
156
Program Wait Insertion Description amended ... according to the settings of WCRH and WCRL.
6.6 Operation Figure 6.17 Example of Idle Cycle Operation (2)
162
Figure 6.17 amended (Before) ICIS1 (After) ICIS0
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Item 8.14.1 Overview
Page 279
Revision (See Manual for Details) Description amended ... Port G pins also function as bus control signal output pins (CS0 to CS3). Figure 8.26 shows ...
8.14.3 Pin Functions
283
Description amended Port G pins also function as bus control signal output pins (CS0 to CS3). The pin functions are different ...
9.7 Usage Notes Figure 9.57 Contention between TCNT Write and Overflow
378
Figure 9.57 amended
TCNT write data TCNT H'FFFF Prohibited TCFV flag M
10.4.1 Interrupt Sources and DTC Activation Table 10.3 8-Bit Timer Interrupt Sources
396
Table 10.3 amended
Channel 0 Interrupt Sour ce CMIA0 CMIB0 OVI0 1 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF
11.2.2 Timer 408 Control/Status Register (TCSR) 409
Description amended ...TCNT, and the timer mode. TCSR is initialized to H'18 by ... Bit 6 description amended
Bit 6 WT/IT I 1 Description Watchdog timer: Generates the WDTOVF signal when TCNT overflows*
12.3.2 Operation in Asynchronous Mode Figure 12.7 Sample Serial Reception Data Flowchart
460
Figure 12.7 amended
Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
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Item 12.3.4 Operation in Clocked Synchronous Mode Figure 12.17 Example of SCI Operation in Transmission
Page 474
Revision (See Manual for Details) Figure 12.17 amended
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
TDRE TEND TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame
13.3.6 Data Transfer Operations Table 13.8 Smart Card Mode Operating States and Interrupt Sources
508
Description of DMAC activation deleted from table 13.8
14.4.3 Input Sampling 529 and A/D Conversion Time Figure 14.5 A/D Conversion Timing
Figure 14.5 amended
(1) Address bus (2)
Write signal
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Item 14.6 Usage Notes Figure 14.9 A/D Conversion Precision Definitions (1)
Page 534
Revision (See Manual for Details) Figure 14.9 amended
Digital output
111 110 101 100 011 010 001 000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 1024 1024
FS
Analog input voltage
15.2.2 D/A Control Register (DACR) 17.5.1 Overview 17.5.3 Programming Precautions
541
Description amended Bits 4 to 0--Reserved: Read-only bits, always read as 1. It cannot be written to.
555 560
Description amended ... within the range H'00000 to H'1FFFF. Description amended The size of ... within the range H'00000 to H'1FFFF. During programming, ... Clearing with an interrupt Description amended When an NMI ...after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are ...
19.6.2 Clearing 580 Software Standby Mode
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Item B.2 Functions
Page 699
Revision (See Manual for Details) TIOR3H--Timer I/O Control Register 3H H'FE82 TPU3 Figure amended TGR3B I/O Control Input capture at TCNT4 count-up/count-down*
1
732 768
Reserved Register H'FF44 Register address amended Serial Status Register H'FF8C Figure amended Parity Error [Clearing condition] When 0 is written to PER after reading PER = 1
791
TIER1--Timer Interrupt Enable Register 1 H'FFE4 TPU1 Figure amended TGR Interrupt Enable A
C.5 Port 5 Block Diagram Figure C.5 (a) Port 5 Block Diagram (Pin P50)
810
Figure C.5 (a) amended
Reset R Q D P50DDR C WDDR5
Appendix H Package Dimensions Figure H.1 TFP-120 Package Dimensions Figure H.2 FP-128 Package Dimensions
844
Figure H.1 replaced
845
Figure H.2 replaced
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Internal data bus
All trademarks and registered trademarks are the property of their respective owners.
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Contents
Section 1 Overview............................................................................................... 1
1.1 1.2 1.3 Overview................................................................................................................................ 1 Block Diagram ....................................................................................................................... 5 Pin Description....................................................................................................................... 7 1.3.1 Pin Arrangement ....................................................................................................... 7 1.3.2 Pin Functions in Each Operating Mode .................................................................. 11 1.3.3 Pin Functions .......................................................................................................... 16
Section 2 CPU..................................................................................................... 23
2.1 Overview.............................................................................................................................. 23 2.1.1 Features................................................................................................................... 23 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 24 2.1.3 Differences from H8/300 CPU ............................................................................... 25 2.1.4 Differences from H8/300H CPU............................................................................. 25 CPU Operating Modes ......................................................................................................... 26 Address Space ...................................................................................................................... 31 Register Configuration ......................................................................................................... 32 2.4.1 Overview................................................................................................................. 32 2.4.2 General Registers .................................................................................................... 33 2.4.3 Control Registers .................................................................................................... 34 2.4.4 Initial Register Values............................................................................................. 36 Data Formats ........................................................................................................................ 37 2.5.1 General Register Data Formats ............................................................................... 37 2.5.2 Memory Data Formats ............................................................................................ 39 Instruction Set ...................................................................................................................... 40 2.6.1 Overview................................................................................................................. 40 2.6.2 Instructions and Addressing Modes........................................................................ 41 2.6.3 Table of Instructions Classified by Function .......................................................... 43 2.6.4 Basic Instruction Formats ....................................................................................... 53 Addressing Modes and Effective Address Calculation ........................................................ 54 2.7.1 Addressing Mode .................................................................................................... 54 2.7.2 Effective Address Calculation ................................................................................ 57 Processing States.................................................................................................................. 61 2.8.1 Overview................................................................................................................. 61 2.8.2 Reset State............................................................................................................... 62 2.8.3 Exception-Handling State ....................................................................................... 63 2.8.4 Program Execution State......................................................................................... 66
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2.2 2.3 2.4
2.5
2.6
2.7
2.8
2.9
2.8.5 Bus-Released State.................................................................................................. 66 2.8.6 Power-Down State .................................................................................................. 66 Basic Timing........................................................................................................................ 67 2.9.1 Overview................................................................................................................. 67 2.9.2 On-Chip Memory (ROM, RAM) ............................................................................ 67 2.9.3 On-Chip Supporting Module Access Timing ......................................................... 69 2.9.4 External Address Space Access Timing ................................................................. 70
Section 3 MCU Operating Modes .......................................................................71
3.1 Overview.............................................................................................................................. 71 3.1.1 Operating Mode Selection ...................................................................................... 71 3.1.2 Register Configuration............................................................................................ 72 Register Descriptions ........................................................................................................... 72 3.2.1 Mode Control Register (MDCR) ............................................................................ 72 3.2.2 System Control Register (SYSCR) ......................................................................... 73 Operating Mode Descriptions .............................................................................................. 75 3.3.1 Mode 1 .................................................................................................................... 75 3.3.2 Mode 2 .................................................................................................................... 75 3.3.3 Mode 3 .................................................................................................................... 75 3.3.4 Mode 4 .................................................................................................................... 75 3.3.5 Mode 5 .................................................................................................................... 76 3.3.6 Mode 6 .................................................................................................................... 76 3.3.7 Mode 7 .................................................................................................................... 76 Pin Functions in Each Operating Mode ............................................................................... 77 Memory Map in Each Operating Mode ............................................................................... 77
3.2
3.3
3.4 3.5
Section 4 Exception Handling .............................................................................85
4.1 Overview.............................................................................................................................. 85 4.1.1 Exception Handling Types and Priority.................................................................. 85 4.1.2 Exception Handling Operation ............................................................................... 86 4.1.3 Exception Vector Table .......................................................................................... 86 Reset..................................................................................................................................... 88 4.2.1 Overview................................................................................................................. 88 4.2.2 Reset Types............................................................................................................. 88 4.2.3 Reset Sequence ....................................................................................................... 89 4.2.4 Interrupts after Reset............................................................................................... 90 4.2.5 State of On-Chip Supporting Modules after Reset Release .................................... 90 Traces................................................................................................................................... 91 Interrupts.............................................................................................................................. 92 Trap Instruction.................................................................................................................... 93
4.2
4.3 4.4 4.5
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4.6 4.7
Stack Status after Exception Handling................................................................................. 94 Notes on Use of the Stack .................................................................................................... 95
Section 5 Interrupt Controller ............................................................................. 97
5.1 Overview.............................................................................................................................. 97 5.1.1 Features................................................................................................................... 97 5.1.2 Block Diagram ........................................................................................................ 98 5.1.3 Pin Configuration.................................................................................................... 99 5.1.4 Register Configuration............................................................................................ 99 Register Descriptions ......................................................................................................... 100 5.2.1 System Control Register (SYSCR) ....................................................................... 100 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................. 101 5.2.3 IRQ Enable Register (IER) ................................................................................... 102 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ...................................... 103 5.2.5 IRQ Status Register (ISR)..................................................................................... 104 Interrupt Sources................................................................................................................ 105 5.3.1 External Interrupts ................................................................................................ 105 5.3.2 Internal Interrupts ................................................................................................. 106 5.3.3 Interrupt Exception Handling Vector Table.......................................................... 106 Interrupt Operation............................................................................................................. 110 5.4.1 Interrupt Control Modes and Interrupt Operation................................................. 110 5.4.2 Interrupt Control Mode 0 ...................................................................................... 113 5.4.3 Interrupt Control Mode 2 ...................................................................................... 115 5.4.4 Interrupt Exception Handling Sequence ............................................................... 117 5.4.5 Interrupt Response Times ..................................................................................... 119 Usage Notes ....................................................................................................................... 121 5.5.1 Contention between Interrupt Generation and Disabling...................................... 121 5.5.2 Instructions That Disable Interrupts...................................................................... 122 5.5.3 Times when Interrupts Are Disabled .................................................................... 122 5.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... 122 DTC Activation by Interrupt.............................................................................................. 123 5.6.1 Overview............................................................................................................... 123 5.6.2 Block Diagram ...................................................................................................... 123 5.6.3 Operation .............................................................................................................. 124
5.2
5.3
5.4
5.5
5.6
Section 6 Bus Controller................................................................................... 127
6.1 Overview............................................................................................................................ 127 6.1.1 Features................................................................................................................. 127 6.1.2 Block Diagram ...................................................................................................... 128 6.1.3 Pin Configuration.................................................................................................. 129
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6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.1.4 Register Configuration.......................................................................................... 130 Register Descriptions ......................................................................................................... 131 6.2.1 Bus Width Control Register (ABWCR)................................................................ 131 6.2.2 Access State Control Register (ASTCR) .............................................................. 132 6.2.3 Wait Control Registers H and L (WCRH, WCRL)............................................... 133 6.2.4 Bus Control Register H (BCRH)........................................................................... 136 6.2.5 Bus Control Register L (BCRL) ........................................................................... 138 Overview of Bus Control ................................................................................................... 139 6.3.1 Area Partitioning................................................................................................... 139 6.3.2 Bus Specifications................................................................................................. 141 6.3.3 Memory Interfaces................................................................................................ 142 6.3.4 Advanced Mode.................................................................................................... 142 6.3.5 Areas in Normal Mode ......................................................................................... 143 6.3.6 Chip Select Signals ............................................................................................... 144 Basic Bus Interface ............................................................................................................ 145 6.4.1 Overview............................................................................................................... 145 6.4.2 Data Size and Data Alignment.............................................................................. 145 6.4.3 Valid Strobes......................................................................................................... 147 6.4.4 Basic Timing......................................................................................................... 148 6.4.5 Wait Control ......................................................................................................... 156 Burst ROM Interface.......................................................................................................... 158 6.5.1 Overview............................................................................................................... 158 6.5.2 Basic Timing......................................................................................................... 158 6.5.3 Wait Control ......................................................................................................... 160 Idle Cycle........................................................................................................................... 161 6.6.1 Operation .............................................................................................................. 161 6.6.2 Pin States in Idle Cycle ......................................................................................... 164 Bus Release........................................................................................................................ 165 6.7.1 Overview............................................................................................................... 165 6.7.2 Operation .............................................................................................................. 165 6.7.3 Pin States in External Bus Released State............................................................. 166 6.7.4 Transition Timing ................................................................................................. 167 6.7.5 Usage Note............................................................................................................ 168 Bus Arbitration................................................................................................................... 168 6.8.1 Overview............................................................................................................... 168 6.8.2 Operation .............................................................................................................. 168 6.8.3 Bus Transfer Timing ............................................................................................. 169 6.8.4 External Bus Release Usage Note......................................................................... 169 Resets and the Bus Controller ............................................................................................ 170
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Section 7 Data Transfer Controller ................................................................... 171
7.1 Overview............................................................................................................................ 171 7.1.1 Features................................................................................................................. 171 7.1.2 Block Diagram ...................................................................................................... 172 7.1.3 Register Configuration.......................................................................................... 173 Register Descriptions ......................................................................................................... 174 7.2.1 DTC Mode Register A (MRA) ............................................................................. 174 7.2.2 DTC Mode Register B (MRB) .............................................................................. 176 7.2.3 DTC Source Address Register (SAR)................................................................... 177 7.2.4 DTC Destination Address Register (DAR) ........................................................... 177 7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 178 7.2.6 DTC Transfer Count Register B (CRB) ................................................................ 178 7.2.7 DTC Enable Registers (DTCER) .......................................................................... 179 7.2.8 DTC Vector Register (DTVECR) ......................................................................... 180 7.2.9 Module Stop Control Register (MSTPCR) ........................................................... 181 Operation............................................................................................................................ 182 7.3.1 Overview............................................................................................................... 182 7.3.2 Activation Sources ................................................................................................ 184 7.3.3 DTC Vector Table................................................................................................. 185 7.3.4 Location of Register Information in Address Space ............................................. 188 7.3.5 Normal Mode........................................................................................................ 189 7.3.6 Repeat Mode ......................................................................................................... 190 7.3.7 Block Transfer Mode ............................................................................................ 191 7.3.8 Chain Transfer ...................................................................................................... 193 7.3.9 Operation Timing.................................................................................................. 194 7.3.10 Number of DTC Execution States ........................................................................ 195 7.3.11 Procedures for Using DTC.................................................................................... 197 7.3.12 Examples of Use of the DTC ................................................................................ 198 Interrupts ............................................................................................................................ 200 Usage Notes ....................................................................................................................... 200
7.2
7.3
7.4 7.5
Section 8 I/O Ports ............................................................................................ 201
8.1 8.2 Overview............................................................................................................................ 201 Port 1.................................................................................................................................. 206 8.2.1 Overview............................................................................................................... 206 8.2.2 Register Configuration.......................................................................................... 207 8.2.3 Pin Functions ........................................................................................................ 209 Port 2.................................................................................................................................. 217 8.3.1 Overview............................................................................................................... 217 8.3.2 Register Configuration.......................................................................................... 217
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8.3
8.3.3 Pin Functions ........................................................................................................ 220 8.4 Port 3.................................................................................................................................. 228 8.4.1 Overview............................................................................................................... 228 8.4.2 Register Configuration.......................................................................................... 228 8.4.3 Pin Functions ........................................................................................................ 231 8.5 Port 4.................................................................................................................................. 233 8.5.1 Overview............................................................................................................... 233 8.5.2 Register Configuration.......................................................................................... 234 8.5.3 Pin Functions ........................................................................................................ 234 8.6 Port 5.................................................................................................................................. 235 8.6.1 Overview............................................................................................................... 235 8.6.2 Register Configuration.......................................................................................... 235 8.6.3 Pin Functions ........................................................................................................ 238 8.7 Port 6.................................................................................................................................. 239 8.7.1 Overview............................................................................................................... 239 8.7.2 Register Configuration.......................................................................................... 240 8.7.3 Pin Functions ........................................................................................................ 242 8.8 Port A................................................................................................................................. 244 8.8.1 Overview............................................................................................................... 244 8.8.2 Register Configuration.......................................................................................... 245 8.8.3 Pin Functions ........................................................................................................ 248 8.8.4 MOS Input Pull-Up Function................................................................................ 250 8.9 Port B ................................................................................................................................. 251 8.9.1 Overview............................................................................................................... 251 8.9.2 Register Configuration.......................................................................................... 252 8.9.3 Pin Functions ........................................................................................................ 255 8.9.4 MOS Input Pull-Up Function................................................................................ 257 8.10 Port C ................................................................................................................................. 258 8.10.1 Overview............................................................................................................... 258 8.10.2 Register Configuration.......................................................................................... 259 8.10.3 Pin Functions ........................................................................................................ 261 8.10.4 MOS Input Pull-Up Function................................................................................ 263 8.11 Port D................................................................................................................................. 264 8.11.1 Overview............................................................................................................... 264 8.11.2 Register Configuration.......................................................................................... 265 8.11.3 Pin Functions ........................................................................................................ 267 8.11.4 MOS Input Pull-Up Function................................................................................ 268 8.12 Port E ................................................................................................................................. 269 8.12.1 Overview............................................................................................................... 269 8.12.2 Register Configuration.......................................................................................... 270
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8.12.3 Pin Functions ........................................................................................................ 272 8.12.4 MOS Input Pull-Up Function................................................................................ 273 8.13 Port F.................................................................................................................................. 274 8.13.1 Overview............................................................................................................... 274 8.13.2 Register Configuration.......................................................................................... 275 8.13.3 Pin Functions ........................................................................................................ 277 8.14 Port G ................................................................................................................................. 279 8.14.1 Overview............................................................................................................... 279 8.14.2 Register Configuration.......................................................................................... 280 8.14.3 Pin Functions ........................................................................................................ 283
Section 9 16-Bit Timer Pulse Unit (TPU)......................................................... 285
9.1 Overview............................................................................................................................ 285 9.1.1 Features................................................................................................................. 285 9.1.2 Block Diagram ...................................................................................................... 289 9.1.3 Pin Configuration.................................................................................................. 290 9.1.4 Register Configuration.......................................................................................... 292 Register Descriptions ......................................................................................................... 294 9.2.1 Timer Control Register (TCR) .............................................................................. 294 9.2.2 Timer Mode Register (TMDR) ............................................................................. 300 9.2.3 Timer I/O Control Register (TIOR) ...................................................................... 302 9.2.4 Timer Interrupt Enable Register (TIER) ............................................................... 319 9.2.5 Timer Status Register (TSR)................................................................................. 322 9.2.6 Timer Counter (TCNT)......................................................................................... 325 9.2.7 Timer General Register (TGR) ............................................................................. 326 9.2.8 Timer Start Register (TSTR)................................................................................. 327 9.2.9 Timer Synchro Register (TSYR) .......................................................................... 328 9.2.10 Module Stop Control Register (MSTPCR) ........................................................... 329 Interface to Bus Master ...................................................................................................... 330 9.3.1 16-Bit Registers .................................................................................................... 330 9.3.2 8-Bit Registers ...................................................................................................... 330 Operation............................................................................................................................ 332 9.4.1 Overview............................................................................................................... 332 9.4.2 Basic Functions..................................................................................................... 333 9.4.3 Synchronous Operation......................................................................................... 339 9.4.4 Buffer Operation ................................................................................................... 341 9.4.5 Cascaded Operation .............................................................................................. 345 9.4.6 PWM Modes ......................................................................................................... 347 9.4.7 Phase Counting Mode ........................................................................................... 352 Interrupts ............................................................................................................................ 358
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9.2
9.3
9.4
9.5
9.6
9.7
9.5.1 Interrupt Sources and Priorities ............................................................................ 358 9.5.2 DTC Activation..................................................................................................... 360 9.5.3 A/D Converter Activation..................................................................................... 360 Operation Timing............................................................................................................... 361 9.6.1 Input/Output Timing ............................................................................................. 361 9.6.2 Interrupt Signal Timing ........................................................................................ 365 Usage Notes ....................................................................................................................... 369
Section 10 8-Bit Timers.....................................................................................379
10.1 Overview............................................................................................................................ 379 10.1.1 Features................................................................................................................. 379 10.1.2 Block Diagram...................................................................................................... 380 10.1.3 Pin Configuration.................................................................................................. 381 10.1.4 Register Configuration.......................................................................................... 382 10.2 Register Descriptions ......................................................................................................... 383 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) .......................................................... 383 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ................................ 383 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................. 384 10.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) ................................................... 384 10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)................................... 387 10.2.6 Module Stop Control Register (MSTPCR) ........................................................... 390 10.3 Operation ........................................................................................................................... 391 10.3.1 TCNT Incrementation Timing .............................................................................. 391 10.3.2 Compare Match Timing........................................................................................ 392 10.3.3 Timing of External RESET on TCNT .................................................................. 394 10.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 394 10.3.5 Operation with Cascaded Connection................................................................... 395 10.4 Interrupts............................................................................................................................ 396 10.4.1 Interrupt Sources and DTC Activation ................................................................. 396 10.4.2 A/D Converter Activation..................................................................................... 396 10.5 Sample Application............................................................................................................ 397 10.6 Usage Notes ....................................................................................................................... 398 10.6.1 Contention between TCNT Write and Clear......................................................... 398 10.6.2 Contention between TCNT Write and Increment ................................................. 399 10.6.3 Contention between TCOR Write and Compare Match ....................................... 400 10.6.4 Contention between Compare Matches A and B .................................................. 401 10.6.5 Switching of Internal Clocks and TCNT Operation ............................................ 401 10.6.6 Usage Note............................................................................................................ 403
Section 11 Watchdog Timer ..............................................................................405
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11.1 Overview............................................................................................................................ 405 11.1.1 Features................................................................................................................. 405 11.1.2 Block Diagram ...................................................................................................... 406 11.1.3 Pin Configuration.................................................................................................. 407 11.1.4 Register Configuration.......................................................................................... 407 11.2 Register Descriptions ......................................................................................................... 408 11.2.1 Timer Counter (TCNT)......................................................................................... 408 11.2.2 Timer Control/Status Register (TCSR) ................................................................. 408 11.2.3 Reset Control/Status Register (RSTCSR) ............................................................. 410 11.2.4 Notes on Register Access...................................................................................... 412 11.3 Operation............................................................................................................................ 414 11.3.1 Watchdog Timer Operation .................................................................................. 414 11.3.2 Interval Timer Operation ...................................................................................... 415 11.3.3 Timing of Setting Overflow Flag (OVF) .............................................................. 416 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) .......................... 417 11.4 Interrupts ............................................................................................................................ 418 11.5 Usage Notes ....................................................................................................................... 418 11.5.1 Contention between Timer Counter (TCNT) Write and Increment ...................... 418 11.5.2 Changing Value of CKS2 to CKS0....................................................................... 418 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................. 419 11.5.4 System Reset by WDTOVF Signal....................................................................... 419 11.5.5 Internal Reset in Watchdog Timer Mode.............................................................. 419
Section 12 Serial Communication Interface (SCI) ........................................... 421
12.1 Overview............................................................................................................................ 421 12.1.1 Features................................................................................................................. 421 12.1.2 Block Diagram ...................................................................................................... 423 12.1.3 Pin Configuration.................................................................................................. 424 12.1.4 Register Configuration.......................................................................................... 425 12.2 Register Descriptions ......................................................................................................... 426 12.2.1 Receive Shift Register (RSR)................................................................................ 426 12.2.2 Receive Data Register (RDR) ............................................................................... 426 12.2.3 Transmit Shift Register (TSR) .............................................................................. 427 12.2.4 Transmit Data Register (TDR).............................................................................. 427 12.2.5 Serial Mode Register (SMR)................................................................................. 428 12.2.6 Serial Control Register (SCR)............................................................................... 431 12.2.7 Serial Status Register (SSR).................................................................................. 435 12.2.8 Bit Rate Register (BRR)........................................................................................ 439 12.2.9 Smart Card Mode Register (SCMR) ..................................................................... 448 12.2.10 Module Stop Control Register (MSTPCR) ........................................................... 449
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12.3 Operation ........................................................................................................................... 450 12.3.1 Overview............................................................................................................... 450 12.3.2 Operation in Asynchronous Mode ........................................................................ 452 12.3.3 Multiprocessor Communication Function ............................................................ 463 12.3.4 Operation in Clocked Synchronous Mode............................................................ 471 12.4 SCI Interrupts..................................................................................................................... 479 12.5 Usage Notes ....................................................................................................................... 481
Section 13 Smart Card Interface........................................................................485
13.1 Overview............................................................................................................................ 485 13.1.1 Features................................................................................................................. 485 13.1.2 Block Diagram...................................................................................................... 486 13.1.3 Pin Configuration.................................................................................................. 487 13.1.4 Register Configuration.......................................................................................... 488 13.2 Register Descriptions ......................................................................................................... 489 13.2.1 Smart Card Mode Register (SCMR) ..................................................................... 489 13.2.2 Serial Status Register (SSR) ................................................................................. 490 13.2.3 Serial Mode Register (SMR)................................................................................. 492 13.2.4 Serial Control Register (SCR)............................................................................... 493 13.3 Operation ........................................................................................................................... 494 13.3.1 Overview............................................................................................................... 494 13.3.2 Pin Connections .................................................................................................... 495 13.3.3 Data Format .......................................................................................................... 496 13.3.4 Register Settings ................................................................................................... 498 13.3.5 Clock..................................................................................................................... 500 13.3.6 Data Transfer Operations...................................................................................... 502 13.3.7 Operation in GSM Mode ...................................................................................... 509 13.4 Usage Notes ....................................................................................................................... 511
Section 14 A/D Converter .................................................................................515
14.1 Overview............................................................................................................................ 515 14.1.1 Features................................................................................................................. 515 14.1.2 Block Diagram...................................................................................................... 516 14.1.3 Pin Configuration.................................................................................................. 517 14.1.4 Register Configuration.......................................................................................... 518 14.2 Register Descriptions ......................................................................................................... 519 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)............................................... 519 14.2.2 A/D Control/Status Register (ADCSR)................................................................. 520 14.2.3 A/D Control Register (ADCR) ............................................................................. 522 14.2.4 Module Stop Control Register (MSTPCR) ........................................................... 523
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14.3 Interface to Bus Master ...................................................................................................... 524 14.4 Operation............................................................................................................................ 525 14.4.1 Single Mode (SCAN = 0) ..................................................................................... 525 14.4.2 Scan Mode (SCAN = 1) ........................................................................................ 527 14.4.3 Input Sampling and A/D Conversion Time .......................................................... 529 14.4.4 External Trigger Input Timing.............................................................................. 530 14.5 Interrupts ............................................................................................................................ 531 14.6 Usage Notes ....................................................................................................................... 531
Section 15 D/A Converter (Not Supported in H8S/2393) ................................ 537
15.1 Overview............................................................................................................................ 537 15.1.1 Features................................................................................................................. 537 15.1.2 Block Diagram ...................................................................................................... 538 15.1.3 Pin Configuration.................................................................................................. 539 15.1.4 Register Configuration.......................................................................................... 539 15.2 Register Descriptions ......................................................................................................... 540 15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)................................................... 540 15.2.2 D/A Control Register (DACR).............................................................................. 540 15.2.3 Module Stop Control Register (MSTPCR) ........................................................... 542 15.3 Operation............................................................................................................................ 543
Section 16 RAM ............................................................................................... 545
16.1 Overview............................................................................................................................ 545 16.1.1 Block Diagram ...................................................................................................... 545 16.1.2 Register Configuration.......................................................................................... 546 16.2 Register Descriptions ......................................................................................................... 546 16.2.1 System Control Register (SYSCR) ....................................................................... 546 16.3 Operation............................................................................................................................ 547 16.4 Usage Note......................................................................................................................... 547
Section 17 ROM ............................................................................................... 549
17.1 Overview............................................................................................................................ 549 17.1.1 Block Diagram ...................................................................................................... 549 17.1.2 Register Configuration.......................................................................................... 550 17.2 Register Descriptions ......................................................................................................... 550 17.2.1 Bus Control Register L (BCRL) ........................................................................... 550 17.3 Operation............................................................................................................................ 551 17.4 PROM Mode ...................................................................................................................... 552 17.4.1 PROM Mode Setting............................................................................................. 552 17.4.2 Socket Adapter and Memory Map ........................................................................ 552
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17.5 Programming ..................................................................................................................... 555 17.5.1 Overview............................................................................................................... 555 17.5.2 Programming and Verification ............................................................................. 555 17.5.3 Programming Precautions..................................................................................... 560 17.5.4 Reliability of Programmed Data ........................................................................... 561
Section 18 Clock Pulse Generator .....................................................................563
18.1 Overview............................................................................................................................ 563 18.1.1 Block Diagram...................................................................................................... 563 18.1.2 Register Configuration.......................................................................................... 563 18.2 Register Descriptions ......................................................................................................... 564 18.2.1 System Clock Control Register (SCKCR) ............................................................ 564 18.3 Oscillator............................................................................................................................ 566 18.3.1 Connecting a Crystal Resonator............................................................................ 566 18.3.2 External Clock Input............................................................................................. 568 18.4 Duty Adjustment Circuit.................................................................................................... 570 18.5 Medium-Speed Clock Divider ........................................................................................... 570 18.6 Bus Master Clock Selection Circuit ................................................................................... 570
Section 19 Power-Down Modes ........................................................................571
19.1 Overview............................................................................................................................ 571 19.1.1 Register Configuration.......................................................................................... 572 19.2 Register Descriptions ......................................................................................................... 573 19.2.1 Standby Control Register (SBYCR) ..................................................................... 573 19.2.2 System Clock Control Register (SCKCR) ............................................................ 575 19.2.3 Module Stop Control Register (MSTPCR) ........................................................... 576 19.3 Medium-Speed Mode......................................................................................................... 577 19.4 Sleep Mode ........................................................................................................................ 578 19.5 Module Stop Mode ............................................................................................................ 578 19.5.1 Module Stop Mode ............................................................................................... 578 19.5.2 Usage Notes .......................................................................................................... 579 19.6 Software Standby Mode..................................................................................................... 580 19.6.1 Software Standby Mode........................................................................................ 580 19.6.2 Clearing Software Standby Mode......................................................................... 580 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.... 581 19.6.4 Software Standby Mode Application Example..................................................... 581 19.6.5 Usage Notes .......................................................................................................... 582 19.7 Hardware Standby Mode ................................................................................................... 583 19.7.1 Hardware Standby Mode ...................................................................................... 583 19.7.2 Hardware Standby Mode Timing.......................................................................... 583
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19.8 Clock Output Disabling Function ................................................................................... 584
Section 20 Electrical Characteristics................................................................. 585
20.1 Absolute Maximum Ratings .............................................................................................. 585 20.2 DC Characteristics ............................................................................................................. 586 20.3 AC Characteristics ............................................................................................................. 593 20.3.1 Clock Timing ........................................................................................................ 594 20.3.2 Control Signal Timing .......................................................................................... 596 20.3.3 Bus Timing ........................................................................................................... 598 20.3.4 Timing of On-Chip Supporting Modules.............................................................. 606 20.4 A/D Conversion Characteristics......................................................................................... 611 20.5 D/A Convervion Characteristics ........................................................................................ 612 20.6 Usage Note......................................................................................................................... 612
Appendix A Instruction Set .............................................................................. 613
A.1 A.2 A.3 A.4 A.5 A.6 Instruction List ................................................................................................................... 613 Instruction Codes ............................................................................................................... 637 Operation Code Map.......................................................................................................... 651 Number of States Required for Instruction Execution ....................................................... 655 Bus States During Instruction Execution ........................................................................... 666 Condition Code Modification ............................................................................................ 680
Appendix B Internal I/O Register ..................................................................... 686
B.1 B.2 Addresses ........................................................................................................................... 686 Functions............................................................................................................................ 693
Appendix C I/O Port Block Diagrams .............................................................. 800
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 C.13 Port 1 Block Diagram ........................................................................................................ 800 Port 2 Block Diagram ........................................................................................................ 802 Port 3 Block Diagram ........................................................................................................ 806 Port 4 Block Diagram ........................................................................................................ 809 Port 5 Block Diagram ........................................................................................................ 810 Port 6 Block Diagram ........................................................................................................ 814 Port A Block Diagram........................................................................................................ 818 Port B Block Diagram........................................................................................................ 821 Port C Block Diagram........................................................................................................ 822 Port D Block Diagram........................................................................................................ 823 Port E Block Diagram ........................................................................................................ 824 Port F Block Diagram ........................................................................................................ 825 Port G Block Diagram........................................................................................................ 833
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Appendix D Pin States.......................................................................................836
D.1 Port States in Each Mode ................................................................................................... 836
Appendix E Pin States at Power-On..................................................................840
E.1 E.2 When Pins Settle from an Indeterminate State at Power-On ............................................. 840 When Pins Settle from the High-Impedance State at Power-On........................................ 841
Appendix F Timing of Transition to and Recovery from Hardware Standby Mode................................................................................842 Appendix G Product Lineup..............................................................................843 Appendix H Package Dimensions .....................................................................844
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1. Overview
Section 1 Overview
1.1 Overview
The H8S/2355 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include data transfer controller (DTC) bus masters, ROM and RAM, a16-bit timer-pulse unit (TPU), 8-bit timer, watchdog timer 1 (WDT), serial communication interface (SCI), A/D converter, D/A converter* , and I/O ports. The on-chip ROM is either PROM (ZTAT * ) or mask ROM, with a capacity of 128, 64 or 32 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Seven operating modes, modes 1 to 7, are provided, and there is a choice of address space and single-chip mode or external expansion mode. The features of the H8S/2355 Group are shown in table 1.1. Notes: 1. The H8S/2393 does not support a D/A converter. 2. ZTAT is a registered trademark of Renesas Technology Corp. There is no PROM version of the H8S/2393.
(R)2
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1. Overview
Table 1.1
Item CPU
Overview
Specification * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns 16 x 16-bit register-register multiply 32 / 16-bit register-register divide * Sixty-five basic instructions 8/16/32-bit move/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions * Two CPU operating modes Normal mode Advanced mode * * * * * * * * * * * * * * : 64-kbyte address space : 16-Mbyte address space : 1000 ns : 1000 ns
Instruction set suitable for high-speed operation
Bus controller
Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins Automatic 2-phase encoder count capability
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
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1. Overview
Item 8-bit timer 2 channels Specification * * * Watchdog timer * Serial communication * interface (SCI) * 3 channels * A/D converter * * * * * * D/A converter* * * I/O ports Memory * * * 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channels High-speed conversion: 6.7 s minimum conversion time (at 20-MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 87 I/O pins, 8 input-only pins PROM or mask ROM High-speed static RAM ROM 128 kbytes 64 kbytes 32 kbytes RAM 4 kbytes 2 kbytes 4 kbytes
Product Name H8S/2355 H8S/2353 H8S/2393 Interrupt controller * * * Power-down state * * * * *
Nine external interrupt pins (NMI, IRQ0 to IRQ7) 47 internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode
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1. Overview
Item modes CPU Mode 1 2 3 4 5 6 7 Advanced Operating Mode Normal Description On-Chip ROM Initial Value 8 bits 8 bits -- 16 bits 8 bits 8 bits -- 16 bits 16 bits 16 bits Maximum Value 16 bits 16 bits Specification External Data Bus
Operating Seven MCU operating modes
On-chip ROM disabled expansion Disabled mode On-chip ROM enabled expansion Enabled mode Single-chip mode Enabled
On-chip ROM disabled expansion Disabled mode On-chip ROM disabled expansion Disabled mode On-chip ROM enabled expansion Enabled mode Single-chip mode Enabled
Clock * Built-in duty correction circuit pulse t Packages * 120-pin plastic TQFP (TFP-120) * 128-pin plastic QFP (FP-128) Product 5-V Version Lineup Operating 5 V 10 % power supply voltage Operating 2 to 20 MHz frequency Mark code HD6472355F20 HD6472355TE20 HD6432355(A**)F Mask HD6432355(A**)TE ROM Version HD6432353(A**)F HD6432353(A**)TE HD6432393(A**)F HD6432393(A**)TE Packages FP-128 TFP-120 ZTAT
3.3-V Version* 3.0 V to 5.5 V
3-V Version 2.7 V to 5.5 V
ROM/RAM (bytes)
2 to 13 MHz -- -- HD6432355(M**)F HD6432355(M**)TE HD6432353(M**)F HD6432353(M**)TE HD6432393(M**)F HD6432393(M**)TE FP-128 TFP-120
2 to 10 MHz HD6472355F10 128 k/4 k HD6472355TE10 HD6432355(K**)F 128 k/4 k HD6432355(K**)TE HD6432353(K**)F 64 k/2 k HD6432353(K**)TE HD6432393(K**)F 32 k/4 k HD6432393(K**)TE FP-128 TFP-120
Note:
Notes: 1. With the mask ROM version, (**) is the ROM code. 2. Please contact Renesas Sales for information on the 3.3-V version. The H8S/2393 does not support a D/A converter.
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1. Overview
1.2
Block Diagram
Figure 1.1 and figure 1.2 show a internal block diagrams of the H8S/2355 and H8S/2353, and the H8S/2393.
PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0
VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS
Port D
Port E
Internal data bus
H8S/2000 CPU
Internal address bus
Bus controller
MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI
Port A
Clock pulse generator
PA7 /A23 /IRQ7 PA6 /A22 /IRQ6 PA5 /A21 /IRQ5 PA4 /A20 /IRQ4 PA3 /A19 PA2 /A18 PA1 /A17 PA0 /A16 PB7 /A15 PB6 /A14 PB5 /A13 PB4 /A12 PB3 / A11 PB2 /A10 PB1 /A9 PB0 /A8 PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 P50 /TxD2 P51 /RxD2 P52 /SCK2 P53 /ADTRG
Interrupt controller PF7 / PF6 /AS PF5 /RD PF4 /HWR PF3 /LWR PF2 /WAIT PF1 /BACK PF0 /BREQ PG4 /CS0 PG3 /CS1 PG2 /CS2 PG1 /CS3 PG0 P67 /CS7/IRQ3 P66 /CS6/IRQ2 P65 /IRQ1 P64 /IRQ0 P63 P62 P61 /CS5 P60 /CS4
DTC
Port B
Peripheral address bus Peripheral data bus
ROM
Port F
WDT
Port C
RAM
Port G
8-bit timer
SCI
Port 3
D/A converter TPU
Port 6
A/D converter
Port 5
Port 1
Port 2
Port 4
P10 / TIOCA0 P11 / TIOCB0 P12 / TIOCC0 / TCLKA P13 / TIOCD0 / TCLKB P14 / TIOCA1 P15 / TIOCB1 / TCLKC P16 / TIOCA2 P17 / TIOCB2 / TCLKD
P20 / TIOCA3 P21 / TIOCB3 P22 / TIOCC3 / T M R I 0 P23 / TIOCD3 / T M C I 0 P24 / TIOCA4 / T M R I 1 P25 / TIOCB4 / T M C I 1 P26 / TIOCA5 / T M O 0 P27 / TIOCB5 / T M O 1
Vref AVCC AVSS
Figure 1.1 Block Diagram (H8S/2355, H8S/2353)
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P47 / AN7/ DA1 P46 / AN6/ DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0
PG4 /CS0 PG3 /CS1 PG2 /CS2 PG1 /CS3 PG0 PF7 / PF6 /AS PF5 /RD PF4 /HWR PF3 /LWR PF2 /WAIT PF1 /BACK PF0 /BREQ
MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI
1. Overview
P67 /CS7/IRQ3 P66 /CS6/IRQ2 P65 /IRQ1 P64 /IRQ0 P63 P62 P61 /CS5 P60 /CS4
Port 6 Port G Port F
Port 1
Clock pulse generator
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Interrupt controller
P10 / TIOCA0 P11 / TIOCB0 P12 / TIOCC0/ TCLKA P13 / TIOCD0/ TCLKB P14 / TIOCA1 P15 / TIOCB1/ TCLKC P16 / TIOCA2 P17 / TIOCB2/ TCLKD
TPU
ROM RAM
VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Port 2
P20 / TIOCA3 P21 / TIOCB3 P22 / TIOCC3/ T M R I 0 P23 / TIOCD3 / T M C I 0 P24 / TIOCA4 / T M R I 1 P25 / TIOCB4 / T M C I 1 P26 / TIOCA5/ T MO 0 P27 / TIOCB5/ T MO 1
H8S/2000 CPU
Port D
DTC
Vref AVCC AVSS
PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8
Internal data bus Internal address bus
WDT
8-bit timer
SCI
A/D converter
Figure 1.2 Block Diagram (H8S/2393)
Port 4
Bus controller
Peripheral data bus Peripheral address bus
Port E
P47 / AN7 P46 / AN6 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Port 5 Port 3
PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0
Port C
Port B
Port A
PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0
PB7 /A15 PB6 /A14 PB5 /A13 PB4 /A12 PB3 / A11 PB2 /A10 PB1 /A9 PB0 /A8
P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0
P50 /TxD2 P51 /RxD2 P52 /SCK2 P53 /ADTRG
PA7 /A23 /IRQ7 PA6 /A22 /IRQ6 PA5 /A21 /IRQ5 PA4 /A20 /IRQ4 PA3 /A19 PA2 /A18 PA1 /A17 PA0 /A16
1. Overview
1.3
1.3.1
Pin Description
Pin Arrangement
Figures 1.3 and 1.4 show the pin arrangement of the H8S/2355 and H8S/2353, and figure 1.5 and 1.6 show the pin arrangement of the H8S/2393.
P51 /RxD2 P50 /TxD2 PF0 / BREQ PF1 / BACK PF2 / WAIT PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 / TIOCA3 P21 / TIOCB3 P22 / TIOCC3 /TMRI0 P23 / TIOCD3 /TMCI0 P24 / TIOCA4 /TMRI1 P25 / TIOCB4 /TMCI1 P26 / TIOCA5 /TMO0 P27 / TIOCB5 /TMO1 P63 P62 P61 / CS5
Figure 1.3 H8S/2355 and H8S/2353 Pin Arrangement (TFP-120: Top View)
VCC PC0 / A0 PC1 / A1 PC2 / A2 PC3 / A3 VSS PC4 / A4 PC5 / A5 PC6 / A6 PC7 / A7 PB0 / A8 PB1 / A9 PB2 / A10 PB3 / A11 VSS PB4 / A12 PB5 / A13 PB6 / A14 PB7 / A15 PA0 / A16 PA1 /A17 PA2 / A18 PA3 / A19 VSS PA4 / A20 / IRQ4 PA5 / A21 / IRQ5 PA6 / A22 / IRQ6 PA7 / A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P52 /SCK2 P53 /ADTRG AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /AN6/DA0 P47 /AN7/DA1 AVSS VSS P17 /TIOCB2/TCLKD P16 /TIOCA2 P15 /TIOCB1/TCLKC P14 /TIOCA1 P13 /TIOCD0/ TCLKB P12 /TIOCC0/ TCLKA P11 /TIOCB0 P10 /TIOCA0 MD0 MD1 MD2 PG0 PG1 /CS3 PG2 /CS2 PG3 /CS1 PG4 /CS0
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P60 /CS4 VSS P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC P64 /IRQ0 P65 /IRQ1
Rev.4.00 Feb. 13, 2007 Page 7 of 846 REJ09B0354-0400
1. Overview
AVCC Vref P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6/ DA0 P47 / AN7/ DA1 AVSS VSS P17 / TIOCB2 / TCLKD P16 / TIOCA2 P15 / TIOCB1 / TCLKC P14 / TIOCA1 P13 / TIOCD0 / TCLKB P12 / TIOCC0 / TCLKA P11 / TIOCB0 P10 / TIOCA0 MD0 MD1 MD2 PG0 PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Rev.4.00 Feb. 13, 2007 Page 8 of 846 REJ09B0354-0400
Figure 1.4 H8S/2355 and H8S/2353 Pin Arrangement (FP-128: Top View)
PG3 /CS1 PG4 /CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 /IRQ4 PA5 /A21 /IRQ5 PA6 /A22 /IRQ6 PA7 /A23 /IRQ7 P67 /CS7/IRQ3 P66 /CS6/IRQ2 VSS VSS P65 /IRQ1 P64 /IRQ0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P53 /ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 /BREQ PF1 /BACK PF2 /WAIT PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 / VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 /TIOCA3 P21 /TIOCB3 P22 /TIOCC3/TMRI0 P23 /TIOCD3/TMCI0 P24 /TIOCA4/TMRI1 P25 /TIOCB4/TMCI1 P26 /TIOCA5/TMO0 P27 /TIOCB5/TMO1 P63 P62 P61 /CS5 VSS VSS P60 /CS4 VSS
1. Overview
P51 / RxD2 P50 / TxD2 PF0 / BREQ PF1 / BACK PF2 / WAIT PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 / TIOCA3 P21 / TIOCB3 P22 / TIOCC3/ T M RI 0 P23 / TIOCD3/ T M CI 0 P24 / TIOCA4/ T M RI 1 P25 / TIOCB4/ T M CI 1 P26 / TIOCA5/ T M O0 P27 / TIOCB5/ T M O1 P63 P62 P61 / CS5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
Figure 1.5 H8S/2393 Pin Arrangement (TFP-120: Top View)
VCC PC0 / A0 PC1 / A1 PC2 / A2 PC3 / A3 VSS PC4 / A4 PC5 / A5 PC6 / A6 PC7 / A7 PB0 / A8 PB1 / A9 PB2 / A10 PB3 / A11 VSS PB4 / A12 PB5 / A13 PB6 / A14 PB7 / A15 PA0 / A16 PA1 / A17 PA2 / A18 PA3 / A19 VSS PA4 / A20 / IRQ4 PA5 / A21 / IRQ5 PA6 / A22 / IRQ6 PA7 / A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P52 /SCK2 P53 /ADTRG AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /AN6 P47 /AN7 AVSS VSS P17 /TIOCB2/TCLKD P16 /TIOCA2 P15 /TIOCB1/TCLKC P14 /TIOCA1 P13 /TIOCD0/TCLKB P12 /TIOCC0/TCLKA P11 /TIOCB0 P10 /TIOCA0 MD0 MD1 MD2 PG0 PG1 /CS3 PG2 /CS2 PG3 /CS1 PG4 /CS0
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P60 / CS4 VSS P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC P64 / IRQ0 P65 / IRQ1
Rev.4.00 Feb. 13, 2007 Page 9 of 846 REJ09B0354-0400
1. Overview
AVCC Vref P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6 P47 / AN7 AVSS VSS P17 / TIOCB2 / TCLKD P16 / TIOCA2 P15 / TIOCB1 / TCLKC P14 / TIOCA1 P13 / TIOCD0 / TCLKB P12 / TIOCC0 / TCLKA P11 / TIOCB0 P10 / TIOCA0 MD0 MD1 MD2 PG0 PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Rev.4.00 Feb. 13, 2007 Page 10 of 846 REJ09B0354-0400
Figure 1.6 H8S/2393 Pin Arrangement (FP-128: Top View)
PG3 / CS1 PG4 / CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 / A20 /IRQ4 PA5 / A21 /IRQ5 PA6 / A22 /IRQ6 PA7 / A23 /IRQ7 P67 / CS7/IRQ3 P66 / CS6/IRQ2 VSS VSS P65 /IRQ1 P64 /IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P53 /ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 /BREQ PF1 /BACK PF2 /WAIT PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 / VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 /TIOCA3 P21 /TIOCB3 P22 /TIOCC3/TMRI0 P23 /TIOCD3/TMCI0 P24 /TIOCA4/TMRI1 P25 /TIOCB4/TMCI1 P26 /TIOCA5/TMO0 P27 /TIOCB5/TMO1 P63 P62 P61 /CS5 VSS VSS P60 /CS4 VSS
1. Overview
1.3.2
Pin Functions in Each Operating Mode
Table 1.2 shows the pin functions of the H8S/2355 Group in each of the operating modes. Table 1.2
Pin No. TFP-120 FP-128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 1 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 PA0 PA1 PA2 PA3 VSS Mode 2 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0 PA1 PA2 PA3 VSS Mode 3 VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 VSS PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 VSS
Pin Functions in Each Operating Mode
Pin Name Mode 4 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS Mode 5 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA5/A21/ IRQ5 Mode 6 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/ IRQ4 PA5/A21/ IRQ5 Mode 7 VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 VSS PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 VSS PROM*1 Mode VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 OE A10 A11 VSS A12 A13 A14 A15 A16 VCC VCC NC VSS
PA4/IRQ4 PA4/IRQ4 PA4/IRQ4 A20 PA5/IRQ5 PA5/IRQ5 PA5/IRQ5 PA5/A21/ IRQ5
PA4/IRQ4 NC PA5/IRQ5 NC
Rev.4.00 Feb. 13, 2007 Page 11 of 846 REJ09B0354-0400
1. Overview
Pin No. TFP-120 FP-128 27 28 29 30 -- -- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Mode 1 Mode 2 Mode 3 Pin Name Mode 4 Mode 5 PA6/A22/ IRQ6 PA7/A23/ IRQ7 Mode 6 PA6/A22/ IRQ6 PA7/A23/ IRQ7 Mode 7 PROM*1 Mode
PA6/IRQ6 PA6/IRQ6 PA6/IRQ6 PA6/A22/ IRQ6 PA7/IRQ7 PA7/IRQ7 PA7/IRQ7 PA7/A23/ IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0 PE1 PE2 PE3 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0
PA6/IRQ6 NC PA7/IRQ7 NC NC NC VSS VSS NC NC VCC NC NC NC NC VSS NC NC NC NC D0 D1 D2 D3 VSS D4 D5 D6 D7 VCC NC
P67/IRQ3/ P67/IRQ3/ P67/IRQ3/ P67/IRQ3 CS7 CS7 CS7 P66/IRQ2/ P66/IRQ2/ P66/IRQ2/ P66/IRQ2 CS6 CS6 CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0 PE1 PE2 PE3 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0
Rev.4.00 Feb. 13, 2007 Page 12 of 846 REJ09B0354-0400
1. Overview
Pin No. TFP-120 FP-128 54 55 56 57 58 59 60 -- -- 61 62 63 64 60 61 62 63 64 65 66 67 68 69 70 71 72 Mode 1 P31/TxD1 Mode 2 P31/TxD1 Mode 3 P31/TxD1 Pin Name Mode 4 P31/TxD1 Mode 5 P31/TxD1 Mode 6 P31/TxD1 Mode 7 P31/TxD1 PROM*1 Mode NC
P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 P32/RxD0 NC P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 NC P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 NC P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 P35/SCK1 NC VSS P60 VSS VSS P61 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI1 P24/ TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS P60 VSS VSS P61 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI1 P24/ TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS P60 VSS VSS P61 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI1 P24/ TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS P60/ CS4 VSS VSS P61/ CS5 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI P24/ TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS P60/ CS4 VSS VSS P61/ CS5 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI1 P24 / TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS P60/ CS4 VSS VSS P61/ CS5 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI1 P24/ TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS P60 VSS VSS P61 P62 P63 P27/ TIOCB5/ TMO1 P26/ TIOCA5/ TMO0 P25/ TIOCB4/ TMCI1 P24/ TIOCA4/ TMRI1 P23/ TIOCD3/ TMCI0 P22/ TIOCC3/ TMRI1 P21/ TIOCB3 P20/ TIOCA3 VSS NC VSS VSS NC NC NC NC
65
73
NC
66
74
NC
67
75
NC
68
76
NC
69
77
NC
70 71
78 79
NC NC
Rev.4.00 Feb. 13, 2007 Page 13 of 846 REJ09B0354-0400
1. Overview
Pin No. TFP-120 FP-128 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 -- -- 91 92 93 94 95 96 97 98 99 100 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Mode 1 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC AS RD HWR LWR Mode 2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC AS RD HWR LWR Mode 3 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC PF6 PF5 PF4 PF3 Pin Name Mode 4 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC AS RD HWR LWR Mode 5 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC AS RD HWR LWR Mode 6 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC AS RD HWR LWR Mode 7 RES NMI STBY VCC XTAL EXTAL VSS PF7/ VCC PF6 PF5 PF4 PF3 PROM*1 Mode
WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC VPP A9 VSS VCC NC NC VSS NC VCC NC NC NC NC CE PGM NC NC
PF2/WAIT PF2/WAIT PF2 PF1/BACK PF1/BACK PF1 PF0/BREQ PF0/BREQ PF0 P50/TxD2 P50/TxD2 P50/TxD2
PF2/WAIT PF2/WAIT PF2/WAIT PF2 PF1/BACK PF1/BACK PF1/BACK PF1 PF0/BREQ PF0/BREQ PF0/BREQ PF0 P50/TxD2 P50/TxD2 P50/TxD2 P50/TxD2
P51/RxD2 P51/RxD2 P51/RxD2 P51/RxD2 P51/RxD2 P51/RxD2 P51/RxD2 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P52/SCK2 P52/SCK2 P52/SCK2 P52/SCK2 P52/SCK2 P52/SCK2 P52/SCK2 NC P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P53/ ADTRG AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 NC VCC VCC NC NC NC NC NC NC
Rev.4.00 Feb. 13, 2007 Page 14 of 846 REJ09B0354-0400
1. Overview
Pin No. TFP-120 FP-128 101 102 103 104 105 111 112 113 114 115 Mode 1 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4/CS0 VSS NC Mode 2 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4/CS0 VSS NC Mode 3 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4 VSS NC Pin Name Mode 4 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 VSS NC Mode 5 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 VSS NC Mode 6 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 VSS NC Mode 7 P46/AN6/ DA0*2 P47/AN7/ DA1*2 AVSS VSS P17/ TIOCB2/ TCLKD P16/ TIOCA2 P15/ TIOCB1/ TCLKC P14/ TIOCA1 P13/ TIOCD0/ TCLKB P12/ TIOCC0/ TCLKA P11/ TIOCB0 P10/ TIOCA0 MD0 MD1 MD2 PG0 PG1 PG2 PG3 PG4 VSS NC PROM*1 Mode NC NC VSS VSS NC
106 107
116 117
NC NC
108 109
118 119
NC NC
110
120
NC
111 112 113 114 115 116 117 118 119 120 -- --
121 122 123 124 125 126 127 128 1 2 3 4
NC NC VSS VSS VSS NC NC NC NC NC VSS NC
Notes: NC pins should be connected to VSS or left open. 1. There is no PROM version of the H8S/2393. 2. As the H8S/2393 does not support a D/A converter, it does not have the DA0 and DA1 outputs. Rev.4.00 Feb. 13, 2007 Page 15 of 846 REJ09B0354-0400
1. Overview
1.3.3
Pin Functions
Table 1.3 outlines the pin functions of the H8S/2355 Group. Table 1.3 Pin Functions
Pin No. Type Power supply Symbol VCC TFP-120 1, 33, 52, 76, 81 6, 15, 24, 38, 47, 59, 79, 104 FP-128 5, 39, 58, 84, 89 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 85 I/O Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V).
VSS
Input
Clock
XTAL
77
Input
Connects to a crystal oscillator. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 18, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input.
EXTAL
78
86
Input
80
88
Output System clock: Supplies the system clock to an external device.
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1. Overview Pin No. Type Symbol TFP-120 115 to 113 FP-128 125 to 123 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2355 Group is operating. MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 RES Operating Mode -- Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
Operating mode MD2 to control MD0
System control
73
81
Input
Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2355 Group.
STBY
75
83
Input
BREQ
88
96
Input
BACK
87
95
Output Bus request acknowledge: Indicates that the bus has been released to an external bus master.
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1. Overview Pin No. Type Interrupts Symbol NMI TFP-120 74 FP-128 82 I/O Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt.
IRQ7 to IRQ0 Address bus A23 to A0
28 to 25, 29 to 32 28 to 25, 23 to 16, 14 to 7, 5 to 2 51 to 48, 46 to 39, 37 to 34
32 to 29, 33, 34, 37, 38 32 to 29, 27 to 20, 18 to 11, 9 to 6 57 to 54, 52 to 45, 43 to 40
Input
Output Address bus: These pins output an address.
Data bus
D15 to D0 CS7 to CS0
I/O
Data bus: These pins constitute a bidirectional data bus.
Bus control
29, 30, 33, 34, Output Chip select: Signals for selecting 61, 60, 69, 66, areas 7 to 0. 117 to 120 127, 128, 1, 2 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space.
AS
RD
83
91
HWR
84
92
LWR
85
93
WAIT
86
94
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1. Overview Pin No. Type 16-bit timerpulse unit (TPU) Symbol TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TFP-120 FP-128 I/O Name and Function Clock input D to A: These pins input an external clock. Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins.
105, 107, 115, 117, Input 109, 110 119, 120 112 to 109 122 to 119 I/O
108, 107
118, 117
I/O
TIOCA2, TIOCB2
106, 105
116, 115
I/O
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
71 to 68
79 to 76
I/O
67, 66
75, 74
I/O
TIOCA5, TIOCB5
65, 64
73, 72
I/O
8-bit timer
TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
65, 64 68, 66
73, 72 76, 74
Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins.
69, 67 72
77, 75 80
Input
Watchdog timer (WDT)
WDTOVF
Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode.
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1. Overview Pin No. Type Serial communication interface (SCI) Smart Card interface Symbol TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1 SCK0 A/D converter AN7 to AN0 ADTRG TFP-120 89, 54, 53 90, 56, 55 91, 58 57 102 to 95 92 FP-128 97, 60, 59 98, 62, 61 101, 64, 63 112 to 105 102 I/O Name and Function
Output Transmit data (channel 0, 1, 2): Data output pins. Input Receive data (channel 0, 1, 2): Data input pins. Serial clock (channel 0, 1, 2): Clock I/O pins. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion.
I/O
Input Input
D/A converter* A/D converter and D/A converters
DA1, DA0 AVCC
102, 101 93
112, 111 103
Output Analog output: D/A converter analog output pins. Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V).
AVSS
103
113
Input
Vref
94
104
Input
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1. Overview Pin No. Type I/O ports Symbol P17 to P10 TFP-120 105 to 112 FP-128 115 to 122 I/O I/O Name and Function Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR).
P27 to P20
64 to 71
72 to 79
I/O
P35 to P30
58 to 53
64 to 59
I/O
P47 to P40 P53 to P50
102 to 95 92 to 89
112 to 105
Input
102, 101, I/O 98, 97
P67 to P60
29 to 32, 63 to 60
33, 34, 37, 38, 71 to 69, 66 32 to 29, 27 to 24
I/O
PA7 to PA0
28 to 25, 23 to 20
I/O
PB7 to PB0
19 to 16, 14 to 11
23 to 20, 18 to 15
I/O
PC7 to PC0
10 to 7, 5 to 2
14 to 11, 9 to 6
I/O
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1. Overview Pin No. Type I/O ports Symbol PD7 to PD0 TFP-120 51 to 48, 46 to 43 FP-128 57 to 54, 52 to 49 I/O I/O Name and Function Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR).
PE7 to PE0
42 to 39, 37 to 34
48 to 45, 43 to 40
I/O
PF7 to PF0
80, 82 to 88
88, 90 to 96
I/O
PG4 to PG0
120 to 116
2, 1, 128 to 126
I/O
Note:
*
The H8S/2393 does not support a D/A converter.
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2. CPU
Section 2 CPU
2.1 Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features
The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:32, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) * High-speed operation All frequently-used instructions execute in one or two states
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2. CPU
Maximum clock rate 8/16/32-bit register-register add/subtract 8 x 8-bit register-register multiply 16 / 8-bit register-register divide 16 x 16-bit register-register multiply 32 / 16-bit register-register divide * Two CPU operating modes Normal mode Advanced mode * Power-down state
: 20 MHz : 50 ns : 600 ns : 600 ns : 1000 ns : 1000 ns
Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of exection states of the MULXU and MULXS instructions.
Internal Operation Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21
There are also differences in the address space, CCR and EXR register functions, power-down state, etc., depending on the product.
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2. CPU
2.1.3
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control register, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast.
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2. CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Normal mode Maximum 64 kbytes, program and data areas combined
CPU operating modes
Advanced mode
Maximum 16-Mbytes for program and data areas combined
Figure 2.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.
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2. CPU
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Power-on reset exception vector Manual reset exception vector
(Reserved for system use)
Exception vector table
Exception vector 1 Exception vector 2
Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.
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2. CPU
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
SP
PC (16 bits)
SP
*2
(SP
)
EXR*1 Reserved*1,*3 CCR CCR*3 PC (16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used.
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2. CPU
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling.
H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved for system use)
H'00000010
Reserved Exception vector 1
Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table.
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2. CPU
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
SP SP Reserved PC (24 bits)
*2
(SP
)
EXR*1 Reserved*1,*3 CCR PC (24 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
Figure 2.5 Stack Structure in Advanced Mode
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2. CPU
2.3
Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be used by the H8S/2355 Group
H'FFFFFFFF (a) Normal Mode (b) Advanced Mode
Figure 2.6 Memory Map
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2. CPU
2.4
2.4.1
Register Configuration
Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers.
General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR) 23 PC 76543210 EXR T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0
Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit*
H: U: N: Z: V: C:
Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag
Note: * In the H8S/2355 Group, this bit cannot be used as an interrupt mask.
Figure 2.7 CPU Registers
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2. CPU
2.4.2
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers
* 16-bit registers E registers (extended registers) (E0 to E7)
* 8-bit registers
ER registers (ER0 to ER7) R registers (R0 to R7)
RH registers (R0H to R7H)
RL registers (R0L to R7L)
Figure 2.8 Usage of General Registers
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2. CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack.
Free area
SP (ER7)
Stack area
Figure 2.9 Stack 2.4.3 Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7--Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3--Reserved: These bits are reserved. They are always read as 1.
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2. CPU
Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2355 Group, this bit cannot be used as an interrupt mask bit. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit
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2. CPU
The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction Set. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
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2. CPU
2.5
Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.10 shows the data formats in general registers.
Data Type Register Number Data Format
1-bit data
RnH
7 0 76543210
Don't care
1-bit data
RnL
Don't care
7 0 76543210
4-bit BCD data
RnH
7 Upper
43 Lower
0 Don't care
4-bit BCD data
RnL
Don't care
7 Upper
43 Lower
0
Byte data
RnH
7 MSB
0 Don't care LSB 7
Don't care
Byte data
RnL
0 LSB
MSB
Figure 2.10 General Register Data Formats
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2. CPU
Data Type Register Number Data Format
Word data
Rn
15 MSB
0 LSB
Word data 15 MSB Longword data 31 MSB
En 0 LSB ERn 16 15 En Rn 0 LSB
Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit
Figure 2.10 General Register Data Formats (cont)
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2. CPU
2.5.2
Memory Data Formats
Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format
Byte data
Address L MSB
LSB
Word data
Address 2M MSB Address 2M + 1 LSB
Longword data
Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB
Figure 2.11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size.
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2. CPU
2.6
2.6.1
Instruction Set
Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV POP* , PUSH* LDM, STM MOVFPE, MOVTPE*
3 1 1
Size BWL WL L B BWL B BWL L BW WL B BWL BWL B --
Types 5
Arithmetic operations
ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS
19
Logic operations Shift Bit manipulation Branch System control Block data transfer
AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* , JMP, BSR, JSR, RTS
2
4 8 14 5 9 1
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- EEPMOV --
Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @- SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2355 Group. Rev.4.00 Feb. 13, 2007 Page 40 of 846 REJ09B0354-0400
2.6.2
Addressing Modes
Table 2.2
Function
#xx
Instruction
Rn
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Data transfer BWL -- -- -- BWL BWL B L BWL B BW BW BWL WL -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- -- -- -- WL BWL BWL BWL BWL B BWL -- BWL -- -- -- --
MOV
BWL
POP, PUSH
--
LDM, STM
--
MOVFPE, MOVTPE*
--
Arithmetic operations
ADD, CMP
BWL
SUB
WL
ADDX, SUBX
B
ADDS, SUBS
--
INC, DEC
--
DAA, DAS
--
--
Instructions and Addressing Modes
MULXU, DIVXU MULXS, DIVXS
--
NEG
--
EXTU, EXTS
--
TAS
--
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use.
Combinations of Instructions and Addressing Modes
Rev.4.00 Feb. 13, 2007 Page 41 of 846 REJ09B0354-0400
Note: * Cannot be used in the H8S/2355 Group.
--
2. CPU
Addressing Modes
2. CPU
Function Instruction
#xx
Rn
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Logic operations AND, OR, XOR NOT -- -- -- -- -- -- -- -- B -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B W W W W -- W -- -- -- B W W W W -- W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B B -- -- -- B B -- B -- BWL -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- --
Shift Bcc, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP
Bit manipulation
Branch
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-- -- -- BW
System control
Block data transfer
Legend: B: Byte W: Word L: Longword
--
2. CPU
2.6.3
Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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2. CPU
Table 2.3
Type Data transfer
Instructions Classified by Function
Instruction MOV Size* B/W/L Function (EAs) Rd, Rs (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2355 Group. Cannot be used in the H8S/2355 Group. @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP +, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
LDM STM
L L
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2. CPU Type Arithmetic operations Instruction ADD SUB Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder.
ADDX SUBX
B
INC DEC
B/W/L
ADDS SUBS DAA DAS
L
B
MULXU
B/W
MULXS
B/W
DIVXU
B/W
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2. CPU Type Arithmetic operations Instruction DIVXS Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
TAS
B
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2. CPU Type Logic operations Instruction AND Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents. Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
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2. CPU Type Bitmanipulation instructions Instruction BSET Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
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2. CPU Type Bitmanipulation instructions Instruction BXOR Size* B Function C ( of ) C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [ ( of )] C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
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2. CPU Type Branch instructions Instruction Bcc Size* -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
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2. CPU Type Instruction Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
System control TRAPA instructions RTE SLEEP LDC
STC
B/W
ANDC
B
ORC
B
XORC
B
NOP
--
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2. CPU Type Block data transfer instruction Instruction EEPMOV.B Size* -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L - 1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4 - 1 R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Note: * Size refers to the operand size. B: Byte W: Word L: Longword
EEPMOV.W
--
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2. CPU
2.6.4
Basic Instruction Formats
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows examples of instruction formats.
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc.
Figure 2.12 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions.
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2. CPU
2.7
2.7.1
Addressing Modes and Effective Address Calculation
Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4
No. 1 2 3 4 5 6 7 8
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
(1) Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added.
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2. CPU
(4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges
Normal Mode 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
Absolute Address Data address
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2. CPU
(6) Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling.
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.13 Branch Address Specification in Memory Indirect Mode
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2. CPU
If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
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No. Effective Address Calculation
Addressing Mode and Instruction Format
Effective Address (EA)
2. CPU
1 Operand is general register contents.
Table 2.6
Register direct (Rn)
op
rm
rn
2 31 24 23 General register contents Don't care 0 31
Register indirect (@ERn)
0
op
r
3 31 General register contents 31 disp 31 Sign extension disp 0 0
Register indirect with displacement @(d:16, ERn) or @(d:32, ERn)
24 23
0
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Effective Address Calculation
op
r
Don't care
4 31 General register contents
Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+
0
31
24 23 Don't care
0
op
r 1, 2, or 4 31 General register contents 31 24 23 Don't care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0
* Register indirect with pre-decrement @-ERn
op
r
No. Effective Address Calculation
Addressing Mode and Instruction Format
Effective Address (EA)
5 31 24 23 abs
Don't care
Absolute address 87 H'FFFF 0
@aa:8
op
@aa:16 31 abs
24 23
Don't care
16 15 Sign extension
0
op
@aa:24 abs
31
24 23
Don't care
0
op
@aa:32 31 abs 24 23
Don't care
op
0
6 IMM
Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data.
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op
2. CPU
2. CPU
No. Effective Address Calculation 23 PC contents 0
Addressing Mode and Instruction Format
Effective Address (EA)
7
Program-counter relative
@(d:8, PC)/@(d:16, PC)
op 23 Sign extension disp 31 24 23
Don't care
disp 0
0
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abs 31 H'000000 87 abs 0 31 24 23
Don't care
8
Memory indirect @@aa:8
* Normal mode
op
16 15 H'00 0
0
15 Memory contents
* Advanced mode abs 31 H'000000 31 Memory contents 87 abs 0 31 24 23
Don't care
op
0
0
2. CPU
2.8
2.8.1
Processing States
Overview
The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions.
Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode
Power-down state CPU operation is stopped to conserve power.*
Software standby mode Hardware standby mode
Note: * The power-down state also includes a medium-speed mode, module stop mode etc.
Figure 2.14 Processing States
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End of bus request
Bus request
Program execution state
End of bus request
Bus request
Bus-released state
End of exception handling
SLEEP instruction with SSBY = 1
SLEEP instruction with SSBY = 0
Request for exception handling
Sleep mode
Interrupt request
Exception-handling state External interrupt RES = high Software standby mode
Reset state*1
STBY = high, RES = low
Hardware standby mode*2 Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.15 State Transitions 2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11, Watchdog Timer.
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2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7
Priority High
Exception Handling Types and Priority
Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is 3 executed*
Trace
End of instruction execution or end of exception-handling 1 sequence* End of instruction execution or end of exception-handling 2 sequence* When TRAPA instruction is executed
Interrupt
Trap instruction Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state.
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(2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address.
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Figure 2.16 shows the stack after exception handling ends.
Normal mode
SP SP CCR CCR* PC (16 bits)
EXR Reserved* CCR CCR* PC (16 bits)
(a) Interrupt control mode 0
(b) Interrupt control mode 2
Advanced mode
SP SP CCR PC (24 bits)
EXR Reserved* CCR PC (24 bits)
(c) Interrupt control mode 0 Note: * Ignored when returning.
(d) Interrupt control mode 2
Figure 2.16 Stack Structure after Exception Handling (Examples)
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2.8.4
Program Execution State
In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 19, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained.
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2.9
2.9.1
Basic Timing
Overview
The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states.
Bus cycle T1 Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address
Read access
Figure 2.17 On-Chip Memory Access Cycle
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Bus cycle T1 Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state
Figure 2.18 Pin States during On-Chip Memory Access
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2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Bus cycle T1 T2
Internal address bus
Address
Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data
Read data
Figure 2.19 On-Chip Supporting Module Access Cycle
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Bus cycle T1 T2
Address bus Unchanged
AS RD HWR, LWR
High
High
High
Data bus
High-impedance state
Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller.
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3. MCU Operating Modes
Section 3 MCU Operating Modes
3.1
3.1.1
Overview
Operating Mode Selection
The H8S/2355 Group has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection
External Data Bus On-Chip Initial ROM Width -- -- 16 bits 16 bits Max. Width
MCU CPU Operating Operating Mode MD2 MD1 MD0 Mode Description 0 1 2 3 4 5 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 -- Normal --
On-chip ROM disabled, Disabled 8 bits expanded mode On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode --
Advanced On-chip ROM disabled, Disabled 16 bits expanded mode 8 bits On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode --
16 bits 16 bits 16 bits
The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2355 Group actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices.
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The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The H8S/2355 Group can be used only in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration
The H8S/2355 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2355 Group. Table 3.2 summarizes these registers. Table 3.2
Name Mode control register System control register Note: *
MCU Registers
Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'01 Address* H'FF3B H'FF39
Lower 16 bits of the address.
3.2
3.2.1
Bit
Register Descriptions
Mode Control Register (MDCR)
: 7 -- 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R
Initial value: R/W :
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2355 Group.
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Bit 7--Reserved: Read-only bit, always read as 1. Bits 6 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. 3.2.2
Bit
System Control Register (SYSCR)
: 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W
Initial value: R/W :
Bit 7--Reserved: Only 0 should be written to this bit. Bit 6--Reserved: Read-only bit, always read as 0. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 --
Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value)
Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value)
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Bit 2--Reserved: Read-only bit, always read as 0. Bit 1--Reserved: Only 0 should be written to this bit. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
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3.3
3.3.1
Operating Mode Descriptions
Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.2 Mode 2
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set. immediately after a reset. Ports B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.4 Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
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3.3.5
Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.7 Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports.
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3.4
Pin Functions in Each Operating Mode
The pin functions of ports A to F vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3
Port Port A PA7 to PA5 PA4 to PA0 Port B Port C Port D Port E Port F PF7 PF6 to PF3 PF2 to PF0 A A D P*/D P/C* C P*/C P*/A P*/A D P*/D P/C* C P*/C P P P P P*/C P
Pin Functions in Each Mode
Mode 1 P Mode 2 P Mode 3 P Mode 4 P*/A A A A D P/D* P/C* C P*/C Mode 5 P*/A A A A D P*/D P/C* C P*/C P*/A P*/A D P*/D P/C* C P*/C P P P P P*/C P Mode 6 P*/A Mode 7 P
Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Note: * After reset
3.5
Memory Map in Each Operating Mode
A memory map of the H8S/2355 is shown in figure 3.1, a memory map of the H8S/2353 in figure 3.2, and a memory map of the H8S/2393 in figure 3.3. The address space is 64 kbytes in modes 1 to 3 (normal modes), and 16 Mbytes in modes 4 to 7 (advanced modes). The on-chip ROM capacity of the H8S/2355 is 128 kbytes, but only 56 kbytes are available in modes 2 and 3 (normal modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus Controller.
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode)
H'0000
On-chip ROM External address space
On-chip ROM
H'EC00 On-chip RAM* H'FC00
External address space
H'DFFF H'E000 External address space H'EC00 On-chip RAM*
H'DFFF
H'EC00 On-chip RAM H'FBFF
H'FC00
External address space
H'FE40 Internal I/O registers H'FF08 External address
space
H'FE40 Internal I/O registers External address H'FF08
space
H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF
H'FF28 Internal I/O registers H'FFFF
H'FF28 Internal I/O registers H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2355
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
External address space
H'00FFFF H'010000 On-chip ROM/ external address space*1
H'00FFFF H'010000 On-chip ROM/ reserved area*2
H'FFEC00 On-chip RAM*3 H'FFFC00
External address space
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3
H'01FFFF
H'FFEC00 On-chip RAM H'FFFBFF
H'FFFC00
External address space
H'FFFE40 Internal I/O registers H'FFFF08 External address
space
H'FFFE40 Internal I/O registers H'FFFF08 External address
space
H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFF28 Internal I/O registers H'FFFFFF
Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. This area is reserved when the EAE bit in BCRL is set to 1, and on-chip ROM when the EAE bit is cleared to 0. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2355 (cont)
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3 (normal single-chip mode)
H'0000
On-chip ROM External address space
On-chip ROM
H'EC00 H'F400
Reserved area On-chip RAM*
H'DFFF H'E000 External address space H'EC00 Reserved area H'F400 On-chip RAM* H'FC00
External address space
H'DFFF
H'F400 H'FBFF On-chip RAM
H'FC00
External address space
H'FE40 Internal I/O registers H'FF08 External address
space
H'FE40 Internal I/O registers External address H'FF08
space
H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF
H'FF28 Internal I/O registers H'FFFF
H'FF28 Internal I/O registers H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.2 Memory Map in Each Operating Mode in the H8S/2353
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
External address space
H'00FFFF H'010000 External address space/reserved area*1
H'00FFFF
H'020000 H'FFEC00 H'FFF400 H'FFFC00 Reserved area On-chip RAM*2
External address space
External address space Reserved area On-chip RAM*2
External address space
H'FFEC00 H'FFF400 H'FFFC00
H'FFF400 H'FFFBFF On-chip RAM
H'FFFE40 Internal I/O registers H'FFFF08 External address
space
H'FFFE40 Internal I/O registers H'FFFF08 External address
space
H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFF28 Internal I/O registers H'FFFFFF
Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.2 Memory Map in Each Operating Mode in the H8S/2353 (cont)
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Mode 1 (normal expanded mode with on-chip ROM disabled)
H'0000
Mode 2 (normal expanded mode with on-chip ROM enabled)
H'0000
Mode 3 (normal single-chip mode)
H'0000
On-chip ROM
On-chip ROM
External address space H'7FFF H'8000 Reserved area H'DFFF H'E000 H'EC00 On-chip H'FBFF H'FC00 H'FE40 H'FF08 H'FF28 H'FFFF RAM*2 H'FBFF H'FC00 H'FE40 H'FF08 H'FF28 H'FFFF H'EC00 On-chip RAM*2 H'FBFF External address space Internal I/O registers External address space Internal I/O registers H'FE40 H'FF07 H'FF28 H'FFFF H'7FFF
External address space H'EC00 On-chip RAM
External address space Internal I/O registers External address space Internal I/O registers
Internal I/O registers
Internal I/O registers
Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.3 Memory Map in Each Operating Mode in the H8S/2393
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode)
H'000000
H'000000
H'000000
On-chip ROM
On-chip ROM
External address space
H'007FFF H'008000
H'007FFF
Reserved area
H'010000
External address space/reserved area*1
H'01FFFF H'020000 H'FFEC00 H'FFEC00
External address space
H'FFEC00
On-chip
H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF
RAM*2
H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF
On-chip
RAM*2
H'FFFBFF
On-chip RAM
External address space
External address space
Internal I/O registers
External address space
Internal I/O registers
External address space
H'FFFE40 H'FFFF07 H'FFFF28 H'FFFFFF
Internal I/O registers
Internal I/O registers
Internal I/O registers
Internal I/O registers
Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0, it is on-chip ROM. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.3 Memory Map in Each Operating Mode in the H8S/2393 (cont)
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4. Exception Handling
Section 4 Exception Handling
4.1
4.1.1
Overview
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low.
1
Trace*
Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception 2 handling ends, if an interrupt request has been issued*
3
Interrupt Low
Trap instruction (TRAPA)* Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state.
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4. Exception Handling
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses.
Power-on reset Manual reset External interrupts: NMI, IRQ7 to IRQ0 Interrupts Internal interrupts: 47 interrupt sources in on-chip supporting modules
Reset Trace Exception sources
Trap instruction
Figure 4.1 Exception Sources In modes 6 and 7 in the H8S/2355, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 128-kbyte area comprising addresses H'000000 to H'01FFFF to be used.
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4. Exception Handling
Table 4.2
Exception Vector Table
Vector Address*
1
Exception Source Power-on reset Manual reset Reserved for system use
Vector Number 0 1 2 3 4
Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0006 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00B6 to H'00B7
Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'016C to H'016F
Trace Reserved for system use External interrupt NMI
5 6 7 8 9 10 11
Trap instruction (4 sources)
Reserved for system use
12 13 14 15
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
2
16 17 18 19 20 21 22 23 24 91
Internal interrupt*
Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table.
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4. Exception Handling
4.2
4.2.1
Reset
Overview
A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2355 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The level of the NMI pin at reset determines whether the type of reset is a power-on reset or a manual reset. The H8S/2355 Group can also be reset by overflow of the watchdog timer. For details see section 11, Watchdog Timer. 4.2.2 Reset Types
A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4.3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4.3 Reset Types
Reset Transition Conditions Type Power-on reset Manual reset NMI High Low RES Low Low CPU Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except for bus controller and I/O ports
A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset.
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4. Exception Handling
4.2.3
Reset Sequence
The H8S/2355 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2355 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2355 Group during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2355 Group starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence.
Prefetch of first program Vector Internal fetch processing instruction
RES Internal address bus Internal read signal Internal write signal Internal data bus (2) (1) (3)
High
(4)
(1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First program instruction
Figure 4.2 Reset Sequence (Modes 2 and 3)
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4. Exception Handling
Internal Prefetch of first processing program instruction * *
Vector fetch
RES Address bus RD HWR, LWR D15 to D0
*
(1)
(3)
(5)
High (2) (4) (6)
(1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * 3 program wait states are inserted.
Figure 4.3 Reset Sequence (Mode 4) 4.2.4 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCR is initialized to H'3FFF and all modules except the DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.
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4. Exception Handling
4.3
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.4 Status of CCR and EXR after Trace Exception Handling
CCR Interrupt Control Mode 0 2 1 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. I UI I2 to I0 EXR T
Trace exception handling cannot be used. -- -- 0
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4. Exception Handling
4.4
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 47 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller.
NMI (1) IRQ7 to IRQ0 (8)
External interrupts Interrupts
Internal interrupts
WDT* (1) TPU (26) 8-bit timer (6) SCI (12) DTC (1) A/D converter (1)
Notes:
Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow.
Figure 4.4 Interrupt Sources and Number of Interrupts
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4. Exception Handling
4.5
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling
CCR Interrupt Control Mode 0 2 I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0
Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution.
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4. Exception Handling
4.6
Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
SP SP CCR CCR* PC (16 bits)
EXR Reserved* CCR CCR* PC (16 bits)
(a) Interrupt control mode 0 Note: * Ignored on return.
(b) Interrupt control mode 2
Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes)
SP SP CCR PC (24 bits)
EXR Reserved* CCR PC (24 bits)
(a) Interrupt control mode 0 Note: * Ignored on return.
(b) Interrupt control mode 2
Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes)
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4. Exception Handling
4.7
Notes on Use of the Stack
When accessing word data or longword data, the H8S/2355 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd.
CCR SP PC
SP
R1L PC
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF
SP
TRAP instruction executed MOV.B R1L, @-ER7
SP set to H'FFFEFF
Data saved above SP
Contents of CCR lost
Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.6 Operation when SP Value is Odd
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5. Interrupt Controller
Section 5 Interrupt Controller
5.1
5.1.1
Overview
Features
The H8S/2355 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. * DTC control DTC activation is performed by means of interrupts.
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5. Interrupt Controller
5.1.2
Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I, UI I2 to I0 Interrupt request Vector number CPU
Internal interrupt request WOVI to TEI
CCR EXR
IPR Interrupt controller
Legend: ISCR IER ISR IPR SYSCR
: IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register
Figure 5.1 Block Diagram of Interrupt Controller
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5. Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller. Table 5.1
Name Nonmaskable interrupt External interrupt requests 7 to 0
Interrupt Controller Pins
Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected
IRQ7 to IRQ0 Input
5.1.4
Register Configuration
Table 5.2 summarizes the registers of the interrupt controller. Table 5.2
Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K
Interrupt Controller Registers
Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2
Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77
Address* H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
1
Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.4.00 Feb. 13, 2007 Page 99 of 846 REJ09B0354-0400
5. Interrupt Controller
5.2
5.2.1
Bit
Register Descriptions
System Control Register (SYSCR)
: 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W
Initial value: R/W :
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller.
Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 --
Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value)
Bit 3--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value)
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5. Interrupt Controller
5.2.2
Bit
Interrupt Priority Registers A to K (IPRA to IPRK)
: 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 -- 0 -- 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W
Initial value: R/W :
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3--Reserved: Read-only bits, always read as 0. Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Note: * 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer --* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 --* SCI channel 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC --* A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2
Reserved bits. These bits cannot be modified and are always read as 1.
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5. Interrupt Controller
As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit : 7 IRQ7E Initial value: R/W : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled.
Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (Initial value)
Note: n = 7 to 0
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5. Interrupt Controller
5.2.4
ISCRH
Bit
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
:
15 0 R/W
14 0 R/W
13 0 R/W
12 0 R/W
11 0 R/W
10 0 R/W
9 0 R/W
8 0 R/W
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W :
ISCRL
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W :
The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input
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5. Interrupt Controller
5.2.5
Bit
IRQ Status Register (ISR)
: 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)*
Initial value: R/W :
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests.
Bit n IRQnF 0 Description [Clearing conditions] (Initial value) * * * * 1 Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1)
[Setting conditions] * * * *
Note: n = 7 to 0
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5. Interrupt Controller
5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (47 sources). 5.3.1 External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2355 Group from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 7 to 0 IRQn interrupt S R Q request
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
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5. Interrupt Controller
Figure 5.3 shows the timing of setting IRQnF.
IRQn input pin
IRQnF
Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts
There are 47 sources for internal interrupts from on-chip supporting modules. * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.
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5. Interrupt Controller
Table 5.4
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of Interrupt Source External pin Vector Address* Vector Normal Number Mode 7 16 17 18 19 20 21 22 23 DTC 24 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 to IPRF4 IPRE2 to IPRE0 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC6 to IPRC4 IPRC2 to IPRC0 IPRD6 to IPRD4 IPR Priority High
Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) Reserved ADI (A/D conversion end) Reserved
Watchdog 25 timer -- A/D -- 26 27 28 29 30 31
TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved
TPU 32 channel 0 33 34 35 36 -- 37 38 39
Low
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5. Interrupt Controller Origin of Interrupt Source Vector Address* Vector Normal Number Mode H'0050 H'0052 H'0054 H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC IPRH2 to IPRH0 IPRH6 to IPRH4 IPRG2 to IPRG0 IPRG6 to IPRG4 IPR IPRF2 to IPRF0 Priority High
Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved
TPU 40 channel 1 41 42 43 TPU 44 channel 2 45 46 47 TPU 48 channel 3 49 50 51 52 -- 53 54 55
TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5)
TPU 56 channel 4 57 58 59 TPU 60 channel 5 61 62 63
Low
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5. Interrupt Controller Origin of Interrupt Source Vector Address* Vector Normal Number Mode H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C IPRI2 to IPRI0 IPR IPRI6 to IPRI4 Priority High
Interrupt Source
CMIA0 (compare match A0) 8-bit timer 64 CMIB0 (compare match B0) channel 0 65 66 OVI0 (overflow 0) Reserved -- 67
CMIA1 (compare match A1) 8-bit timer 68 CMIB1 (compare match B1) channel 1 69 70 OVI1 (overflow 1) 71 72 73 74 75 76 77 78 79 ERI0 (receive error 0) SCI 80 RXI0 (reception completed 0) channel 0 81 TXI0 (transmit data empty 0) 82 TEI0 (transmission end 0) 83 ERI1 (receive error 1) SCI RXI1 (reception completed 1) channel 1 TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) SCI RXI2 (reception completed 2) channel 2 TXI2 (transmit data empty 2) TEI2 (transmission end 2) Note: * 84 85 86 87 88 89 90 91 Reserved --
IPRJ2 to IPRJ0
IPRK6 to IPRK4
IPRK2 to IPRK0 Low
Lower 16 bits of the start address.
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5. Interrupt Controller
5.4
5.4.1
Interrupt Operation
Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2355 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU's CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes
Interrupt Mask Bits Description I -- I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited
SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 -- 2 1 0 0 1 0 -- -- IPR
--
1
--
--
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5. Interrupt Controller
Figure 5.4 shows a block diagram of the priority decision circuit.
Interrupt control mode 0
I
Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number
IPR
I2 to I0
Interrupt control mode 2
Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 2 Legend: * : Don't care * Selected Interrupts All interrupts NMI interrupts All interrupts
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5. Interrupt Controller
(2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2)
Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0).
Interrupt Control Mode 0 2
(3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Acceptance Control I 8-Level Control I2 to I0 IPR Default Priority Determination
Interrupt Setting Control INTM1 INTM0 Mode
T (Trace)
0 2
0 1
0 0
IM X --*
1
X
-- IM
--* PR
2
-- T
Legend: : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. -- : Not used. Rev.4.00 Feb. 13, 2007 Page 112 of 846 REJ09B0354-0400
5. Interrupt Controller Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting.
5.4.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
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5. Interrupt Controller
Program execution status
Interrupt generated? Yes Yes
No
NMI No No
I=0 Yes
Hold pending
No IRQ0 Yes No
IRQ1 Yes
TEI2 Yes
Save PC and CCR I1 Read vector address
Branch to interrupt handling routine
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0
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5. Interrupt Controller
5.4.3
Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
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5. Interrupt Controller
Program execution status
Interrupt generated? Yes Yes NMI No No
No
Level 7 interrupt? Yes Mask level 6 or below? Yes
Level 6 interrupt? No Yes Mask level 5 or below? Yes
No
Level 1 interrupt? No Yes
No
Mask level 0 Yes
No
Save PC, CCR, and EXR
Hold pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2
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5. Interrupt Controller
5.4.4
Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
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Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation
5. Interrupt Controller
Interrupt level determination Wait for end of instruction
Interrupt service routine instruction prefetch
Interrupt request signal
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(1)
(7) (9)
Internal address bus (3) (5)
(11)
(13)
Internal read signal
Internal write signal (2) (4) (6)
(8) (10) (12) (14)
Figure 5.7 Interrupt Exception Handling
Internal data us
(1)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4
(6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine
5. Interrupt Controller
5.4.5
Interrupt Response Times
The H8S/2355 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times
Normal Mode No. 1 2 3 4 5 6 Execution Status Interrupt priority determination*
1
Advanced Mode INTM1 = 0 3 1 to 19 + 2 SI 2 SK 2 SI 2 SI 2 12 to 32 INTM1 = 1 3 1 to 19 + 2 SI 2 SI 2 SI 2 13 to 33 3 SK
INTM1 = 0 3
INTM1 = 1 3 1 to 19 + 2 SI 3 SK SI 2 SI 2 12 to 32
Number of wait states until executing 1 to 2 instruction ends* 19 + 2 SI PC, CCR, EXR stack save Vector fetch Instruction fetch*
3 4
2 SK SI 2 SI 2 11 to 31
Internal processing*
Total (using on-chip memory) Notes: 1. 2. 3. 4.
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch.
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5. Interrupt Controller
Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m 16 Bit Bus 2-State Access 2 3-State Access 3+m
Legend: m : Number of wait states in an external device access.
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5. Interrupt Controller
5.5
5.5.1
Usage Notes
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5.8 shows and example in which the CMIEA bit in 8-bit timer TCR is cleared to 0.
TCR write cycle by CPU CMIA exception handling
Internal address bus
TCR address
Internal write signal
CMIEA
CMFA
CMIA interrupt signal
Figure 5.8 Contention between Interrupt Generation and Disabling
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5. Interrupt Controller
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions That Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
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5. Interrupt Controller
5.6
5.6.1
DTC Activation by Interrupt
Overview
The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 7, Data Transfer Controller. 5.6.2 Block Diagram
Figure 5.9 shows a block diagram of the DTC interrupt controller.
DTC activation request vector number
Interrupt request IRQ interrupt Interrupt source clear signal
Selection circuit Select signal Clear signal DTCER
Control logic Clear signal
DTC
On-chip supporting module
DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0
Figure 5.9 Interrupt Control for DTC
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5. Interrupt Controller
5.6.3
Operation
The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source: Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCEA to DTCEF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities.
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5. Interrupt Controller
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCEA to DTCEF in the DTC and the DISEL bit of MRB in the DTC. Table 5.11 Interrupt Source Selection and Clearing Control
Settings DTC DTCE 0 1 DISEL * 0 1 Interrupt Source Selection/Clearing Control DTC X CPU
X
Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care
(4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit.
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6. Bus Controller
Section 6 Bus Controller
6.1 Overview
The H8S/2355 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features
The features of the bus controller are listed below. * Manages external address space in area units In advanced mode, manages the external space as 8 areas of 2-Mbytes In normal mode, manages the external space as a single area Bus specifications can be set independently for each area * Basic bus interface Chip select (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC * Other features External bus release function
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6. Bus Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS0 to CS7 Area decoder Internal address bus
ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Bus controller Internal data bus Internal control signals Bus mode signal
WAIT
Wait controller
WCRH WCRL
CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal
Figure 6.1 Block Diagram of Bus Controller
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6. Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the pins of the bus controller. Table 6.1
Name Address strobe Read High write Low write Chip select 0 to 7 Wait Bus request Bus request acknowledge
Bus Controller Pins
Symbol AS RD HWR LWR CS0 to CS7 WAIT BREQ BACK I/O Output Output Output Output Output Input Input Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that areas 0 to 7 are selected. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released.
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6. Bus Controller
6.1.4
Register Configuration
Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers
Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL R/W R/W R/W R/W R/W R/W R/W Power-On Reset H'FF/H'00* H'FF H'FF H'FF H'D0 H'3C
2
Manual Reset Retained Retained Retained Retained Retained Retained
Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5
1
Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode.
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6. Bus Controller
6.2
6.2.1
Bit
Register Descriptions
Bus Width Control Register (ABWCR)
: 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W
Modes 1 to 3, 5 to 7 Initial value : 1 RW Mode 4 Initial value : RW : 0 R/W : R/W
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1, 2, 3, and 5, 6, 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode, only part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit access or 16-bit access .
Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access
Note: n = 7 to 0
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6. Bus Controller
6.2.2
Bit
Access State Control Register (ASTCR)
: 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W
Initial value : R/W :
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. In normal mode, only part of area 0 is enabled, and the AST0 bit selects whether external space is to be designated for 2-state access or 3-state access. Wait state insertion is enabled or disabled at the same time.
Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value)
Note: n = 7 to 0
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6. Bus Controller
6.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area is 0 is enabled, and bits W01 and W00 select the number of program wait states for the external space. The settings of bits W71, W70 to W11, and W10 have no effect on operation. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH
Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value)
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6. Bus Controller
Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value)
Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value)
Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1.
Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value)
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6. Bus Controller
(2) WCRL
Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value)
Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1.
Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value)
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Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value)
Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1.
Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value)
6.2.4
Bit
Bus Control Register H (BCRH)
: 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W
BRSTRM BRSTS1 BRSTS0
Initial value : R/W :
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode.
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Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value)
Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed .
Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value)
Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space .
Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value)
Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface.
Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value)
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Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value)
Bits 2 to 0--Reserved: Only 0 should be written to these bits. 6.2.5
Bit
Bus Control Register L (BCRL)
: 7 BRLE 0 R/W 6 -- 0 R/W 5 EAE 1 R/W 4 -- 1 R/W 3 -- 1 R/W 2 -- 1 R/W 1 -- 0 R/W 0 WAITE 0 R/W
Initial value : R/W :
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ and BACK can be used as I/O ports. (Initial value) External bus release is enabled.
Bit 6--Reserved: Only 0 should be written to this bit. Bit 5--External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode.
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6. Bus Controller Bit 5 EAE 0 1 Note: * Description Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2355) or a reserved area* (in the H8S/2353) Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode) (Initial value) Reserved areas should not be accessed.
Bits 4 to 2--Reserved: Only 1 should be written to these bits. Bit 1--Reserved: Only 0 should be written to this bit. Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value)
6.3
6.3.1
Overview of Bus Control
Area Partitioning
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area.
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H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF
H'0000
H'FFFF
(1)
Advanced mode
(2)
Normal mode
Figure 6.2 Overview of Area Partitioning
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6.3.2
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area.
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Table 6.3
ABWCR ABWn 0
Bus Specifications for Each Area (Basic Bus Interface)
ASTCR ASTn 0 1 WCRH, WCRL Wn1 -- 0 Wn0 -- 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 8 2 3 0 0 1 2 3
1
0 1
-- 0
-- 0 1
1
0 1
6.3.3
Memory Interfaces
The H8S/2355 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on, and a burst ROM interface (for area 0 only) that allows direct connection of burst ROM. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. 6.3.4 Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4 and 6.5) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0.
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Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space. When area 1 to 6 external space is accessed, the CS1 to CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. 6.3.5 Areas in Normal Mode
In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expansion mode the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. When external space is accessed, the CS0 signal can be output. The basic bus interface or burst ROM interface can be selected.
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6.3.6
Chip Select Signals
The H8S/2355 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal can be output. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a poweron reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7. For details, see section 8, I/O Ports.
Bus cycle T1 T2 T3
Address bus
Area n external address
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)
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6.4
6.4.1
Basic Bus Interface
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle
Word size
Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space)
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16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address
Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space)
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6.4.3
Valid Strobes
Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4
Area 8-bit access space
Data Buses Used and Valid Strobes
Access Read/ Size Write Byte Read Write Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid
16-bit access Byte space
HWR, LWR Valid
Notes: Hi-Z: High impedance. Invalid: Input state; input value is ignored.
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6.4.4
Basic Timing
8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle T1 T2
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR Write D15 to D8
High
Valid
D7 to D0
High impedance
Note: n = 0 to 7
Figure 6.6 Bus Timing for 8-Bit 2-State Access Space
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8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted.
Bus cycle T1 T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR High
LWR Write D15 to D8
Valid High impedance
D7 to D0 Note: n = 0 to 7
Figure 6.7 Bus Timing for 8-Bit 3-State Access Space
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16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Bus cycle T1 T2
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR Write D15 to D8
High
Valid
D7 to D0
High impedance
Note: n = 0 to 7
Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
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Bus cycle T1 T2
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR Write D15 to D8 High impedance
D7 to D0
Valid
Note: n = 0 to 7
Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
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Bus cycle T1 T2
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0
Valid
Note: n = 0 to 7
Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
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16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Bus cycle T1 T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR High
LWR Write D15 to D8
Valid High impedance
D7 to D0 Note: n = 0 to 7
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
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Bus cycle T1 T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR Write D15 to D8 High impedance
D7 to D0 Note: n = 0 to 7
Valid
Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
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Bus cycle T1 T2 T3
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0 Note: n = 0 to 7
Valid
Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
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6. Bus Controller
6.4.5
Wait Control
When accessing external space, the H8S/2355 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas.
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Figure 6.14 shows an example of wait state insertion timing.
By program wait T1 T2 Tw By WAIT pin Tw Tw T3
WAIT
Address bus
AS
RD Read Data bus Read data
HWR, LWR Write Data bus Write data
Note:
indicates the timing of WAIT pin sampling.
Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset.
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6.5
6.5.1
Burst ROM Interface
Overview
With the H8S/2355 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6.15 (a) and (b). The timing shown in figure 6.15 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.15 (b) is for the case where both these bits are cleared to 0.
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Full access T1 T2 T3 T1 Burst access T2 T1 T2
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6.15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
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Full access T1 T2 Burst access T1 T1
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 6.15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle.
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6.6
6.6.1
Idle Cycle
Operation
When the H8S/2355 Group accesses external space , it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6.16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A Address bus CS (area A) CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2
Long output floating time (a) Idle cycle not inserted (ICIS1 = 0)
Figure 6.16 Example of Idle Cycle Operation (1)
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(2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A Address bus CS (area A) CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS0 = 1) T1 T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD HWR Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2
Long output floating time (a) Idle cycle not inserted (ICIS0 = 0)
Figure 6.17 Example of Idle Cycle Operation (2)
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(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.18. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A Address bus CS (area A) CS (area B) RD T1 T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2
Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1)
Figure 6.18 Relationship between Chip Select (CS) and Read (RD)
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6.6.2
Pin States in Idle Cycle
Table 6.5 shows pin states in an idle cycle. Table 6.5
Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR
Pin States in Idle Cycle
Pin State Contents of next bus cycle High impedance High High High High High
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6.7
6.7.1
Bus Release
Overview
The H8S/2355 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. 6.7.2 Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2355 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. In the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low)
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6. Bus Controller
6.7.3
Pin States in External Bus Released State
Table 6.6 shows pin states in the external bus released state. Table 6.6
Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR
Pin States in Bus Released State
Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance
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6. Bus Controller
6.7.4
Transition Timing
Figure 6.19 shows the timing for transition to the bus-released state.
CPU cycle
CPU cycle T0 T1 T2
External bus released state
High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR
BREQ
BACK
Minimum 1 state [1] [2] [3] [4] [5]
[1] [2] [3] [4] [5]
Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle.
Figure 6.19 Bus-Released State Transition Timing
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6. Bus Controller
6.7.5
Usage Note
When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep mode.
6.8
6.8.1
Bus Arbitration
Overview
The H8S/2355 Group has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.8.2 Operation
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low)
An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low)
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6. Bus Controller
6.8.3
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A-5, Bus States During Instruction Execution, for timings at which the bus is not transferred. * If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 6.8.4 External Bus Release Usage Note
External bus release can be performed on completion of an external bus cycle. The RD signal and CS0 to CS7 signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD and CS0 to CS7 signals may change from the low level to the high-impedance state.
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6. Bus Controller
6.9
Resets and the Bus Controller
In a power-on reset, the H8S/2355, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller's registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored and write data is not guaranteed.
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7. Data Transfer Controller
Section 7 Data Transfer Controller
7.1 Overview
The H8S/2355 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features
* Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode.
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7. Data Transfer Controller
7.1.2
Block Diagram
Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Internal address bus Interrupt controller DTC
Register information
On-chip RAM
CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR
DTC service request
: DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register
Figure 7.1 Block Diagram of DTC
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MRA MRB CRA CRB DAR SAR
Interrupt request
Control logic
DTCERA to DTCERF
DTVECR
Internal data bus
7. Data Transfer Controller
7.1.3
Register Configuration
Table 7.1 summarizes the DTC registers. Table 7.1
Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register
DTC Registers
Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W --* --* --* --* --* --*
2 2 2 2 2 2
Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF
Address* --* --* --* --* --* --*
3 3 3 3 3 3
1
R/W R/W R/W
H'FF30 to H'FF35 H'FF37 H'FF3C
Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0.
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7. Data Transfer Controller
7.2
7.2.1
Register Descriptions
DTC Mode Register A (MRA)
MRA is an 8-bit register that controls the DTC operating mode.
Bit : 7 SM1 Initial value : R/W : Undefined -- 6 SM0 Undefined -- 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined --
Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1)
Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1)
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7. Data Transfer Controller
Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode --
Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area
Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer
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7. Data Transfer Controller
7.2.2
Bit
DTC Mode Register B (MRB)
: 7 CHNE Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- Undefined --
Initial value: R/W :
MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed.
Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred)
Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer.
Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0)
Bits 5 to 0--Reserved: These bits have no effect on DTC operation in the H8S/2355 Group, and should always be written with 0.
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7. Data Transfer Controller
7.2.3
Bit
DTC Source Address Register (SAR)
: 23 22 21 20 19 4 3 2 1 0
Initial value: R/W :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined ----------
Unde- Unde- Unde- Unde- Undefined fined fined fined fined ----------
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4
Bit
DTC Destination Address Register (DAR)
: 23 22 21 20 19 4 3 2 1 0
Initial value : R/W :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined ----------
Unde- Unde- Unde- Unde- Undefined fined fined fined fined ----------
DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address.
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7. Data Transfer Controller
7.2.5
Bit
DTC Transfer Count Register A (CRA)
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: R/W :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRAH CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 7.2.6
Bit
DTC Transfer Count Register B (CRB)
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: R/W :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined --------------------------------
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
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7. Data Transfer Controller
7.2.7
Bit
DTC Enable Registers (DTCER)
: 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W
Initial value: R/W :
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--DTC Activation Enable (DTCEn)
Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] * * 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value)
DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended
Note: n = 7 to 0
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.
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7. Data Transfer Controller
7.2.8
Bit
DTC Vector Register (DTVECR)
: 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W :
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1.
Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] * * * When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation (Initial value)
Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
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7. Data Transfer Controller
7.2.9
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 14--Module Stop (MSTP14): Specifies the DTC module stop mode.
Bit 14 MSTP14 0 1 Description DTC module stop mode cleared DTC module stop mode set (Initial value)
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7. Data Transfer Controller
7.3
7.3.1
Operation
Overview
When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 7.2 shows a flowchart of DTC operation.
Start
Read DTC vector Next transfer
Read register information
Data transfer
Write register information
CHNE = 1 No
Yes
Transfer Counter = 0 or DISEL = 1 No Clear an activation flag
Yes
Clear DTCER
End
Interrupt exception handling
Figure 7.2 Flowchart of DTC Operation
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7. Data Transfer Controller
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 7.2 outlines the functions of the DTC. Table 7.2 DTC Functions
Address Registers Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible * Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues * Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Activation Source * * * * * * IRQ TPU TGI 8-bit timer CMI SCI TXI or RXI A/D converter ADI Software Transfer Source 24 bits Transfer Destination 24 bits
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7. Data Transfer Controller
7.3.2
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 7.3 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 7.3 Activation Source and DTCER Clearance
When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt
When the DISEL Bit Is 0 and the Specified Number of Activation Source Transfers Have Not Ended Software activation The SWDTE bit is cleared to 0
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7. Data Transfer Controller
Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller.
Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request
Selection circuit
DTC
DTVECR
Interrupt controller Interrupt mask
CPU
Figure 7.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. 7.3.3 DTC Vector Table
Figure 7.4 shows the correspondence between DTC vector addresses and register information. Table 7.4 shows the correspondence between activation, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM.
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7. Data Transfer Controller
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400 + (DTVECR [6:0] <<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A
Interrupt Source Write to DTVECR
DTCE* --
Priority High
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ADI (A/D conversion end) TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C (GR0C compare match/ input capture) TGI0D (GR0D compare match/ input capture) TGI1A (GR1A compare match/ input capture) TGI1B (GR1B compare match/ input capture) TGI2A (GR2A compare match/ input capture) TGI2B (GR2B compare match/ input capture)
External pin
16 17 18 19 20 21 22 23
DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 Low
A/D TPU channel 0
28 32 33 34 35
TPU channel 1
40 41
TPU channel 2
44 45
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7. Data Transfer Controller Origin of Interrupt Source TPU channel 3
Interrupt Source TGI3A (GR3A compare match/ input capture) TGI3B (GR3B compare match/ input capture) TGI3C (GR3C compare match/ input capture) TGI3D (GR3D compare match/ input capture) TGI4A (GR4A compare match/ input capture) TGI4B (GR4B compare match/ input capture) TGI5A (GR5A compare match/ input capture) TGI5B (GR5B compare match/ input capture) CMIA0 CMIB0 CMIA1 CMIB1 RXI0 (reception complete 0) TXI0 (transmit data empty 0) RXI1 (reception complete 1) TXI1 (transmit data empty 1) RXI2 (reception complete 2) TXI2 (transmit data empty 2) Note: *
Vector Number 48 49 50 51
Vector Address H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A H'0480 H'0482 H'0488 H'048A H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4
DTCE* DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6
Priority High
TPU channel 4
56 57
TPU channel 5
60 61
8-bit timer channel 0 8-bit timer channel 1 SCI channel 0 SCI channel 1 SCI channel 2
64 65 68 69 81 82 85 86 89 90
Low
DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
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7. Data Transfer Controller
DTC vector address
Register information start address
Register information
Chain transfer
Figure 7.4 Correspondence between DTC Vector Address and Register Information 7.3.4 Location of Register Information in Address Space
Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF).
Lower address Register information start address 0 MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3
Chain transfer
Figure 7.5 Location of Register Information in Address Space
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7. Data Transfer Controller
7.3.5
Normal Mode
In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. Table 7.5
Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B
Register Information in Normal Mode
Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used
SAR Transfer
DAR
Figure 7.6 Memory Mapping in Normal Mode
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7. Data Transfer Controller
7.3.6
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in repeat mode. Table 7.6
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Information in Repeat Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count (8 bits x 2) Not used
SAR or DAR
Repeat area Transfer
DAR or SAR
Figure 7.7 Memory Mapping in Repeat Mode
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7. Data Transfer Controller
7.3.7
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory mapping in block transfer mode. Table 7.7
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Information in Block Transfer Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Designates transfer source address Designates destination address Holds block size Designates block size count Transfer count
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7. Data Transfer Controller
First block
SAR or DAR
* * *
Block area Transfer
DAR or SAR
Nth block
Figure 7.8 Memory Mapping in Block Transfer Mode
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7. Data Transfer Controller
7.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows the memory map for chain transfer.
Source
Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source
Destination
Figure 7.9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected.
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7. Data Transfer Controller
7.3.9
Operation Timing
Figures 7.10 to 7.12 show an example of DTC operation timing.
DTC activation request DTC request Data transfer Vector read Address Transfer information read
Read Write
Transfer information write
Figure 7.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
DTC activation request DTC request
Vector read Address Transfer information read
Data transfer
Read Write Read Write
Transfer information write
Figure 7.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
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7. Data Transfer Controller
DTC activation request DTC request Data transfer Vector read Address Transfer information read
Read Write Read Write
Data transfer
Transfer Transfer information information write read
Transfer information write
Figure 7.12 DTC Operation Timing (Example of Chain Transfer) 7.3.10 Number of DTC Execution States
Table 7.8 lists execution statuses for a single DTC data transfer, and table 7.9 shows the number of states required for each execution status. Table 7.8 DTC Execution Statuses
Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3
Mode Normal Repeat Block transfer
Legend: N: Block size (initial setting of CRAH and CRAL)
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7. Data Transfer Controller
Table 7.9
Number of States Required for Each Execution Status
OnChip RAM 32 1 SI SJ -- 1 OnChip ROM 16 1 1 -- On-Chip I/O Registers 8 2 -- -- 16 2 -- --
Object to be Accessed Bus width Access states Vector read
Execution status
External Devices 8 2 4 -- 3 -- 16 2 -- 3 3+m --
6 + 2m 2
Register information read/write Byte data read Word data read Byte data write Word data write Internal operation
SK SK SL SL SM
1 1 1 1 1
1 1 1 1
2 4 2 4
2 2 2 2
2 4 2 4
3+m 3+m
2 2
3+m 3+m 3+m 3+m
6 + 2m 2 6 + 2m 2
The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I SI + (J SJ + K SK + L SL) + M SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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7. Data Transfer Controller
7.3.11
Procedures for Using DTC
Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested.
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7. Data Transfer Controller
7.3.12
Examples of Use of the DTC
(1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing.
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7. Data Transfer Controller
(2) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing.
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7. Data Transfer Controller
7.4
Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.5
Usage Notes
Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.
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8. I/O Ports
Section 8 I/O Ports
8.1 Overview
The H8S/2355 Group has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 8.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E have a built-in MOS input pull-up function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports A to E can drive a single TTL load and 90-pF capacitive load, and ports 1, 2, 3, 5, 6, F, and G can drive a single TTL load and 30-pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, and A to C can drive an LED (10 mA sink current). Port 2, and ports 64 to 67 and A4 to A7, are Schmitt-triggered inputs. For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
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8. I/O Ports
Table 8.1
Port Port 1 *
Port Functions
Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
Description 8-bit I/O port
P17/TIOCB2/ 8-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TCLKD TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) P16/TIOCA2 P15/TIOCB1/ TCLKC P14/TIOCA1 P13/TIOCD0/ TCLKB P12/TIOCC0/ TCLKA P11/TIOCB0 P10/TIOCA0
Port 2 *
8-bit I/O port
*
P27/TIOCB5/ 8-bit I/O port also functioning as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TMO1 TIOCA4, TIOCB4, TIOCA5, TIOCB5), and 8-bit timer (channels 0 and 1) I/O pins P26/TIOCA5/ (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1) TMO0 P25/TIOCB4/ TMCI1 P24/TIOCA4/ TMRI1 P23/TIOCD3/ TMCI0 P22/TIOCC3/ TMRI0 P21/TIOCB3 P20/TIOCA3
Schmitttriggered input
Port 3 *
6-bit I/O port
P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 P47/AN7/ 1 DA1* P46/AN6/ 1 DA0* P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
6-bit I/O port also functioning as SCI (channels 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1)
*
Open-drain output capability
Port 4 *
8-bit input port
8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1 and DA0)*1
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8. I/O Ports
Port Port 5 * Description 4-bit I/O port Pins P53/ADTRG P52/SCK2 P51/RxD2 P50/TxD2 Port 6 * 8-bit I/O port * Schmitttriggered input (P64 to P67) P67/IRQ3/ CS7 P66/IRQ2/ CS6 P65/IRQ1 P64/IRQ0 P63 P62 P61/CS5 P60/CS4 Port A * 8-bit I/O port * Built-in MOS input pull-up * Open-drain output capability * Schmitttriggered input (PA4 to PA7) PA3/A19 to PA0/A16 I/O port Address output PA4/A20/ IRQ4 Address output PA7/A23/ IRQ7 PA6/A22/ IRQ6 PA5/A21/ IRQ5 Dual function as I/O ports and interrupt input pins (IRQ7 to IRQ4) When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ5) When DDR = 1: address output When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ4) When DDR = 1: address output When DDR I/O port = 0 (after reset): input ports When DDR = 1: address output Dual function as I/O port and interrupt input pins (IRQ7 to IRQ4) 8-bit I/O port also functioning as interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also functioning as bus control output pins (CS4 to CS7), and interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also functioning as interrupt input pins (IRQ0 to IRQ3) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
4-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) and A/D converter input pin (ADTRG)
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8. I/O Ports
Port Port B * Description 8-bit I/O port * Built-in MOS input pull-up Pins PB7/A15 to PB0/A8 Mode 1 Address output Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
When DDR I/O port = 0 (after reset): input port When DDR = 1: address output
Address output
When DDR I/O port = 0 (after reset): input port When DDR = 1: address output
Port C *
8-bit I/O port
PC7/A7 to PC0/A0
Address output
*
Built-in MOS input pull-up
When DDR I/O port = 0 (after reset): input port When DDR = 1: address output
Address output
When DDR I/O port = 0 (after reset): input port When DDR = 1: address output
Port D *
8-bit I/O port
PD7/D15 to PD0/D8
Data bus input/ output
I/O port
Data bus input/output
I/O port
*
Built-in MOS input pull-up
Port E *
8-bit I/O port
PE7/D7 to PE0/D0
In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output
I/O port
In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output
I/O port
*
Built-in MOS input pull-up
Port F *
8-bit I/O port
PF7/
When DDR = 0: input port When DDR = 1 (after reset): output
When DDR When DDR = 0: input port = 0 (after When DDR = 1 (after reset): reset): output input port When DDR = 1: output I/O port AS, RD, HWR, LWR output
When DDR = 0 (after reset): input port When DDR = 1: output I/O port
PF6/AS PF5/RD PF4/HWR PF3/LWR
AS, RD, HWR, LWR output
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8. I/O Ports
Port Description 8-bit I/O port Pins PF2/WAIT Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 I/O port
Port F *
When WAITE = 0 (after I/O port reset): I/O port When WAITE = 1: WAIT input
When WAITE = 0 (after reset): I/O port When WAITE = 1: WAIT input
PF1/BACK PF0/BREQ
When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output
When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output I/O port When DDR = 0*2: input port When DDR = 1* : CS0 output
3
Port G *
5-bit I/O port
PG4/CS0
When DDR= 0*2: input port When DDR= 1*3: CS0 output
I/O port
PG3/CS1 PG2/CS2 PG1/CS3
I/O port
When DDR = 0 (after reset): input port When DDR = 1: CS1, CS2, CS3 output I/O port
PG0
Notes: 1. As the H8S/2393 does not support a D/A converter, it does not have the DA0 and DA1 outputs. 2. After a reset in mode 2 or 6 3. After a reset in mode 1, 4 or 5
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8. I/O Ports
8.2
8.2.1
Port 1
Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2). Port 1 pin functions are the same in all operating modes. Figure 8.1 shows the port 1 pin configuration.
Port 1 pins P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input)
Port 1
P14 (I/O)/TIOCA1 (I/O) P13 (I/O)/TIOCD0 (I/O)/TCLKB (input) P12 (I/O)/TIOCC0 (I/O)/TCLKA (input) P11 (I/O)/TIOCB0 (I/O) P10 (I/O)/TIOCA0 (I/O)
Figure 8.1 Port 1 Pin Functions
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8. I/O Ports
8.2.2
Register Configuration
Table 8.2 shows the port 1 register configuration. Table 8.2
Name Port 1 data direction register Port 1 data register Port 1 register Note: *
Port 1 Registers
Abbreviation P1DDR P1DR PORT1 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB0 H'FF60 H'FF50
Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W :
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the TPU is initialized by a manual reset, the pin states are determined by the P1DDR and P1DR specifications. Port 1 Data Register (P1DR)
Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
Port 1 Register (PORT1)
Bit : 7 P17 Initial value : R/W : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R
Note: * Determined by state of pins P17 to P10.
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
8.2.3
Pin Functions
Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2). Port 1 pin functions are shown in table 8.3. Table 8.3
Pin P17/TIOCB2/ TCLKD
Port 1 Pin Functions
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bits TPSC2 to TPSC0 in TCR0 and TCR5, and bit P17DDR. TPU Channel 2 Setting Table Below (1) Table Below (2) P17DDR Pin function -- TIOCB2 output 0 P17 input
2
1 P17 output
1
TIOCB2 input *
TCLKD input * Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. TPU Channel 2 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx -- -- (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2)
B'0000, B'01xx
CCLR1, CCLR0 Output function
-- --
-- --
Other than B'10 PWM mode 2 output
B'10 --
Legend: x: Don't care
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8. I/O Ports Pin P16/TIOCA2 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, and bit P16DDR. TPU Channel 2 Setting P16DDR Pin function Note: Table Below (1) -- TIOCA2 output Table Below (2) 0 P16 input 1 P16 output
1
TIOCA2 input *
1. TIOCA2 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 = 1.
TPU Channel 2 Setting MD3 to MD0 IOA3 to IOA0
(2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx -- --
(2) B'001x
(1) B'0011
(1) B'0011
(2)
CCLR1, CCLR0 Output function
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- Output compare output --
Other than B'xx00
Other than B'01 PWM PWM mode 1 mode 2 2 output * output
--
B'01 --
Legend: x: Don't care Note: 2. TIOCB2 output is disabled.
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8. I/O Ports Pin P15/TIOCB1/ TCLKC Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, and bit P15DDR. TPU Channel 1 Setting P15DDR Pin function Table Below (1) -- TIOCB1 output Table Below (2) 0 1 P15 input TCLKC input *
2
P15 output
1
TIOCB1 input *
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000, B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. TPU Channel 1 Setting MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0000, B'01xx B'0010 -- B'0000 B'0001 to B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- -- (2) B'xx00 (1) (2) B'0011 Other than B'xx00
CCLR1, CCLR0 Output function
--
--
Output compare output
--
--
Other than B'10 PWM mode 2 output
B'10
--
Legend: x: Don't care
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8. I/O Ports Pin P14/TIOCA1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, and bit P14DDR. TPU Channel 1 Setting P14DDR Pin function Note: Table Below (1) -- TIOCA1 output Table Below (2) 0 P14 input 1 P14 output
1
TIOCA1 input *
1. TIOCA1 input when MD3 to MD0 = B'0000, B'01xx, IOA3 to IOA0 = B'10xx.
TPU Channel 1 Setting MD3 to MD0 IOA3 to IOA0
(2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx -- --
(2) B'001x
(1) B'0010 Other than B'xx00 --
(1) B'0011
(2)
CCLR1, CCLR0 Output function
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- Output compare output --
Other than B'xx00
Other than B'01 PWM PWM mode 1 mode 2 2 output* output
B'01 --
Legend: x: Don't care Note: 2. TIOCB1 output is disabled.
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8. I/O Ports Pin P13/TIOCD0/ TCLKB Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR2, and bit P13DDR. TPU Channel 0 Setting P13DDR Pin function Table Below (1) -- TIOCD0 output Table Below (2) 0 1 P13 input TCLKB input *
2
P13 output
1
TIOCD0 input *
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, IOD3 to IOD0 =B'10xx. 2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101; TCLKB input when channels 1 and 5 are set to phase counting mode. TPU Channel 0 Setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx -- B'0001 to B'0011 B'0101 to B'0111 -- (1) (2) B'0010 -- (2) B'xx00 (1) B'0011 (2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
--
Output compare output
--
--
Other than B'110 PWM mode 2 output
B'110
--
Legend: x: Don't care
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8. I/O Ports Pin P12/TIOCC0/ TCLKA Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR5, and bit P12DDR. TPU Channel 0 Setting P12DDR Pin function Table Below (1) -- TIOCC0 output Table Below (2) 0 1 P12 input TCLKA input *
2
P12 output
1
TIOCC0 input *
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to TPSC0 = B'100; TCLKA input when channels 1 and 5 are set to phase counting mode. TPU Channel 0 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'001x B'0000 B'0001 to B'xx00 B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- -- (2) (1) (1) (1) (2) B'0010 B'0011 Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Output compare output
--
PWM mode 1 3 output*
Other than B'101 PWM mode 2 output
B'101
--
Legend: x: Don't care Note: 3. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies.
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8. I/O Ports Pin P11/TIOCB0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, and bit P11DDR. TPU Channel 0 Setting P11DDR Pin function Note: * Table Below (1) -- TIOCB0 output 0 P11 input Table Below (2) 1 P11 output
TIOCB0 input * TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx.
TPU Channel 0 Setting MD3 to MD0 IOB3 to IOB0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Other than B'010 PWM mode 2 output
B'010
--
Output compare output
--
--
--
Legend: x: Don't care
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8. I/O Ports Pin P10/TIOCA0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, and bit P10DDR. TPU Channel 0 Setting P10DDR Pin function Note: Table Below (1) -- TIOCA0 output 0 P10 input
1
Table Below (2) 1 P10 output
TIOCA0 input *
1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx.
TPU Channel 0 Setting MD3 to MD0 IOA3 to IOA0
CCLR2 to CCLR0 Output function
(1) (2) B'0000 B'001x B'0000 B'0001 to B'xx00 B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- --
(2)
(1) (1) (2) B'0010 B'0011 Other than B'xx00
--
--
Output compare output
--
PWM mode 1 2 output*
Other than B'001 PWM mode 2 output
B'001
--
Legend: x: Don't care Note: 2. TIOCB0 output is disabled.
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8. I/O Ports
8.3
8.3.1
Port 2
Overview
Port 2 is an 8-bit I/O port. Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 8.2 shows the port 2 pin configuration.
Port 2 pins P27 (I/O)/TIOCB5 (I/O)/TMO1 (output) P26 (I/O)/TIOCA5 (I/O)/TMO0 (output) P25 (I/O)/TIOCB4 (I/O)/TMCI1 (input) Port 2 P24 (I/O)/TIOCA4 (I/O)/TMRI1 (input) P23 (I/O)/TIOCD3 (I/O)/TMCI0 (input) P22 (I/O)/TIOCC3 (I/O)/TMRI0 (input) P21 (I/O)/TIOCB3 (I/O) P20 (I/O)/TIOCA3 (I/O)
Figure 8.2 Port 2 Pin Functions 8.3.2 Register Configuration
Table 8.4 shows the port 2 register configuration. Table 8.4
Name Port 2 data direction register Port 2 data register Port 2 register Note: *
Port 2 Registers
Abbreviation P2DDR P2DR PORT2 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB1 H'FF61 H'FF51
Lower 16 bits of the address.
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8. I/O Ports
Port 2 Data Direction Register (P2DDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : R/W :
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the TPU and 8-bit timer are initialized by a manual reset, the pin states are determined by the P2DDR and P2DR specifications. Port 2 Data Register (P2DR)
Bit : 7 P27DR Initial value : R/W : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
Port 2 Register (PORT2)
Bit : 7 P27 Initial value : R/W : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R 3 P23 --* R 2 P22 --* R 1 P21 --* R 0 P20 --* R
Note: * Determined by state of pins P27 to P20.
PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
8.3.3
Pin Functions
Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 8.5. Table 8.5
Pin P27/TIOCB5/ TMO1
Port 2 Pin Functions
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bits OS3 to OS0 in TCSR1, and bit P27DDR. OS3 to OS0 TPU Channel 5 Setting P27DDR Pin function Table Below (1) -- TIOCB5 output All 0 Table Below (2) 0 P27 input 1 P27 output TIOCB5 input * Note: * TIOCB5 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1. Any 1 -- -- TMO1 output
TPU Channel 5 Setting MD3 to MD0 IOB3 to IOB0
(2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx -- -- B'0001 to B'0011 B'0101 to B'0111 -- Output compare output
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR1, CCLR0 Output function
-- --
-- --
Other than B'10 PWM mode 2 output
B'10 --
Legend: x:Don't care
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8. I/O Ports Pin P26/TIOCA5/ TMO0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bits OS3 to OS0 in TCSR0, and bit P26DDR. OS3 to OS0 TPU Channel 5 Setting P26DDR NDER6 Pin function Table Below (1) -- -- TIOCA5 output All 0 Table Below (2) 0 -- P26 input 1 0 P26 output TIOCA5 input * Note:
1
Any 1 -- -- -- TMO0 output
1. TIOCA5 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 = 1.
TPU Channel 5 Setting MD3 to MD0 IOA3 to IOA0
CCLR1, CCLR0 Output function
(2) (1) (2) B'0000, B'01xx B'001x B'0000 B'0001 to B'xx00 B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- -- -- Output compare output --
(1) (1) (2) B'0010 B'0011 Other than B'xx00
-- PWM mode 1 2 output*
Other than B'01 PWM mode 2 output
B'01 --
Legend: x: Don't care Note: 2. TIOCB5 output is disabled.
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8. I/O Ports Pin P25/TIOCB4/ TMCI1 Selection Method and Pin Functions This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P25DDR. TPU Channel 4 Setting P25DDR Pin function Table Below (1) -- TIOCB4 output Table Below (2) 0 P25 input TMCI1 input Note: * TIOCB4 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 to IOB0 = B'10xx. 1 P25 output
TIOCB4 input *
TPU Channel 4 Setting MD3 to MD0 IOB3 to IOB0
(2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx -- -- B'0001 to B'0011 B'0101 to B'0111 -- Output compare output
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR1, CCLR0 Output function
-- --
-- --
Other than B'10 PWM mode 2 output
B'10 --
Legend: x: Don't care
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8. I/O Ports Pin P24/TIOCA4/ TMRI1 Selection Method and Pin Functions This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P24DDR. TPU Channel 4 Setting P24DDR Pin function Table Below (1) -- TIOCA4 output Table Below (2) 0 P24 input TMRI1 input Note: 1. TIOCA4 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 to IOA0 = B'10xx. 1 P24 output
1
TIOCA4 input *
TPU Channel 4 Setting MD3 to MD0 IOA3 to IOA0
(2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx -- --
(2) B'001x
(1) B'0010
(1) B'0011
(2)
CCLR1, CCLR0 Output function
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- Output compare output --
Other than B'xx00
Other than B'01 PWM PWM mode 1 mode 2 2 output* output
--
B'01 --
Legend: x: Don't care Note: 2. TIOCB4 output is disabled.
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8. I/O Ports Pin P23/TIOCD3/ TMCI0 Selection Method and Pin Functions This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P23DDR. TPU Channel 3 Setting P23DDR Pin function Table Below (1) -- TIOCD3 output Table Below (2) 0 P23 input TMCI0 input Note: * TIOCD3 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. 1 P23 output
TIOCD3 input *
TPU Channel 3 Setting MD3 to MD0 IOD3 to IOD0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
--
Output compare output
--
--
Other than B'110 PWM mode 2 output
B'110
--
Legend: x: Don't care
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8. I/O Ports Pin P22/TIOCC3/ TMCI0 Selection Method and Pin Functions This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P22DDR. TPU Channel 3 Setting P22DDR Pin function Table Below (1) -- TIOCC3 output Table Below (2) 0 P22 input TMRI0 input Note: 1. TIOCC3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 1 P22 output
1
TIOCC3 input *
TPU Channel 3 Setting MD3 to MD0 IOC3 to IOC0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1)
(2) B'001x
(1) B'0010
(1) B'0011
(2)
CCLR2 to CCLR0 Output function
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- --
Other than B'xx00
--
--
Output compare output
--
PWM mode 1 2 output*
Other than B'101 PWM mode 2 output
B'101
--
Legend: x: Don't care Note: 2. TIOCD3 output is disabled. When BFA = 1 or BFB = 1 in TMDR3, output is disabled and setting (2) applies.
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8. I/O Ports Pin P21/TIOCB3 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P21DDR. TPU Channel 3 Setting P21DDR Pin function Note: * Table Below (1) -- TIOCB3 output Table Below (2) 0 P21 input 1 P21 output
TIOCB3 input * TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx.
TPU Channel 3 Setting MD3 to MD0 IOB3 to IOB0
CCLR2 to CCLR0 Output function
(1) (2) B'0000 B'0010 B'0000 B'0001 to -- B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- --
(2)
(2) B'xx00
(1) (2) B'0011 Other than B'xx00
--
--
Output compare output
--
--
Other than B'010 PWM mode 2 output
B'010
--
Legend: x: Don't care
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8. I/O Ports Pin P20/TIOCA3 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P20DDR. TPU Channel 3 Setting P20DDR Pin function Note: Table Below (1) -- TIOCA3 output Table Below (2) 0 P20 input 1 P20 output
1
TIOCA3 input *
1. TIOCA3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx.
TPU Channel 3 Setting MD3 to MD0 IOA3 to IOA0
CCLR2 to CCLR0 Output function
(1) (2) B'0000 B'001x B'0000 B'0001 to B'xx00 B'0100 B'0011 B'1xxx B'0101 to B'0111 -- -- --
(2)
(1) (1) (2) B'0010 B'0011 Other than B'xx00
--
--
Output compare output
--
PWM mode 1 2 output*
Other than B'001 PWM mode 2 output
B'001
--
Legend: x: Don't care Note: 2. TIOCB3 output is disabled.
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8. I/O Ports
8.4
8.4.1
Port 3
Overview
Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 8.3 shows the port 3 pin configuration.
Port 3 pins
P35 (I/O)/ SCK1 (I/O) P34 (I/O)/ SCK0 (I/O) Port 3 P33 (I/O)/ RxD1 (input) P32 (I/O)/ RxD0 (input) P31 (I/O)/ TxD1 (output) P30 (I/O)/ TxD0 (output)
Figure 8.3 Port 3 Pin Functions 8.4.2 Register Configuration
Table 8.6 shows the port 3 register configuration. Table 8.6
Name Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register
Port 3 Registers
Abbreviation P3DDR P3DR PORT3 P3ODR R/W W R/W R R/W Initial Value* H'00 H'00 Undefined H'00
2
Address* H'FEB2 H'FF62 H'FF52 H'FF76
1
Notes: 1. Lower 16 bits of the address. 2. Value of bits 5 to 0.
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8. I/O Ports
Port 3 Data Direction Register (P3DDR)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Undefined Undefined
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications. Port 3 Data Register (P3DR)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W
Undefined Undefined
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
Port 3 Register (PORT3)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 P35 --* R 4 P34 --* R 3 P33 --* R 2 P32 --* R 1 P31 --* R 0 P30 --* R
Undefined Undefined
Note: * Determined by state of pins P35 to P30.
PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after a manual reset, and in software standby mode. Port 3 Open Drain Control Register (P3ODR)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Undefined Undefined
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
8.4.3
Pin Functions
Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are shown in table 8.7. Table 8.7
Pin P35/SCK1
Port 3 Pin Functions
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR. CKE1 C/A CKE0 P35DDR Pin function Note: * 0 P35 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK1 input pin
P35 SCK1 SCK1 output pin* output pin* output pin*
When P35ODR = 1, the pin becomes an NMOS open-drain output.
P34/SCK0
The pin function is switched as shown below according to the combination of bit C/A in the SCI0 SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 C/A CKE0 P34DDR Pin function Note: * 0 P34 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK0 input pin
P34 SCK0 SCK0 output pin* output pin* output pin*
When P34ODR = 1, the pin becomes an NMOS open-drain output.
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8. I/O Ports Pin P33/RxD1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE P33DDR Pin function Note: P32/RxD0 * 0 P33 input pin 0 1 P33 output pin* 1 -- RxD1 input pin
When P33ODR = 1, the pin becomes an NMOS open-drain output.
The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR. RE P32DDR Pin function Note: * 0 P32 input pin 0 1 P32 output pin* 1 -- RxD0 input pin
When P32ODR = 1, the pin becomes an NMOS open-drain output.
P31/TxD1
The pin function is switched as shown below according to the combination of bit TE in the SCI1 SCR, and bit P31DDR. TE P31DDR Pin function Note: * 0 P31 input pin 0 1 P31 output pin* 1 -- TxD1 output pin
When P31ODR = 1, the pin becomes an NMOS open-drain output.
P30/TxD0
The pin function is switched as shown below according to the combination of bit TE in the SCI0 SCR, and bit P30DDR. TE P30DDR Pin function Note: * 0 P30 input pin 0 1 P30 output pin* 1 -- TxD0 output pin
When P30ODR = 1, the pin becomes an NMOS open-drain output.
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8.5
8.5.1
Port 4
Overview
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1) in the H8S/2355 and H8S/2353, and as A/D converter analog input pins (AN0 to AN7) in the H8S/2393. Port 4 pin functions are the same in all operating modes. Figure 8.4 shows the port 4 pin configuration.
Port 4 pins P47 (input)/ AN7 (input)/DA1* (output) P46 (input)/ AN6 (input)/DA0* (output) P45 (input)/ AN5 (input) Port 4 P44 (input)/ AN4 (input) P43 (input)/ AN3 (input) P42 (input)/ AN2 (input) P41 (input)/ AN1 (input) P40 (input)/ AN0 (input) Note: * As the H8S/2393 does not support a D/A converter, it does not have the DA0 and DA1 outputs.
Figure 8.4 Port 4 Pin Functions
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8. I/O Ports
8.5.2
Register Configuration
Table 8.8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 8.8
Name Port 4 register
Port 4 Registers
Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FF53
Note: * Lower 16 bits of the address.
Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Bit : 7 P47 Initial value : R/W : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R
Note: * Determined by state of pins P47 to P40.
8.5.3
Pin Functions
* H8S/2355 and H8S/2353 Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). * H8S/2393 Port 4 pins also function as A/D converter analog input pins (AN0 to AN7).
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8.6
8.6.1
Port 5
Overview
Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2) and the A/D converter input pin (ADTRG). Port 5 pin functions are the same in all operating modes. Figure 8.5 shows the port 5 pin configuration.
Port 5 pins
P53 (I/O)/ ADTRG (input) Port 5 P52 (I/O)/ SCK2 (I/O) P51 (I/O)/ RxD2 (input) P50 (I/O)/ TxD2 (output)
Figure 8.5 Port 5 Pin Functions 8.6.2 Register Configuration
Table 8.9 shows the port 5 register configuration. Table 8.9
Name Port 5 data direction register Port 5 data register Port 5 register
Port 5 Registers
Abbreviation P5DDR P5DR PORT5 R/W W R/W R Initial Value* H'0 H'0 Undefined
2
Address* H'FEB4 H'FF64 H'FF54
1
Notes: 1. Lower 16 bits of the address. 2. Value of bits 3 to 0.
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Port 5 Data Direction Register (P5DDR)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 W 2 0 W 1 0 W 0 0 W
P53DDR P52DDR P51DDR P50DDR
Undefined Undefined Undefined Undefined
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be read. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized, the pin states are determined by the P5DDR and P5DR specifications. Port 5 Data Register (P5DR)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 P50DR 0 R/W
Undefined Undefined Undefined Undefined
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P53 to P50). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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Port 5 Register (PORT5)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P53 --* R 2 P52 --* R 1 P51 --* R 0 P50 --* R
Undefined Undefined Undefined Undefined
Note: * Determined by state of pins P53 to P50.
PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 5 pins (P53 to P50) must always be performed on P5DR. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT5 contents are determined by the pin states, as P5DDR and P5DR are initialized. PORT5 retains its prior state after a manual reset, and in software standby mode.
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8.6.3
Pin Functions
Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), and the A/D converter input pin (ADTRG). Port 5 pin functions are shown in table 8.10. Table 8.10 Port 5 Pin Functions
Pin P53/ADTRG Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D converter ADCR, and bit P53DDR. P53DDR Pin function Note: P52/SCK2 * 0 P53 input pin ADTRG input pin* ADTRG input when TRGS0 = TRGS1 = 1. 1 P53 output pin
The pin function is switched as shown below according to the combination of bit C/A in the SCI2 SMR, bits CKE0 and CKE1 in SCR, and bit P52DDR. CKE1 C/A CKE0 P52DDR Pin function 0 P52 input pin 0 1 P52 output pin 0 1 -- SCK2 output pin 0 1 -- -- SCK2 output pin 1 -- -- -- SCK2 input pin
P51/RxD2
The pin function is switched as shown below according to the combination of bit RE in the SCI2 SCR, and bit P51DDR. RE P51DDR Pin function 0 P51 input pin 0 1 P51 output pin 1 -- RxD2 input pin
P50/TxD2
The pin function is switched as shown below according to the combination of bit TE in the SCI2 SCR, and bit P50DDR. TE P50DDR Pin function 0 P50 input pin 0 1 P50 output pin 1 -- TxD2 output pin
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8.7
8.7.1
Port 6
Overview
Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3) and bus control output pins (CS4 to CS7). The functions of pins P65 to P62 are the same in all operating modes, while the functions of pins P67, P66, P61, and P60 change according to the operating mode. Pins P67 to P64 are schmitt-triggered inputs. Figure 8.6 shows the port 6 pin configuration.
Port 6 pins P67/IRQ3/CS7 P66/IRQ2/CS6 P65/IRQ1 Port 6 P64/IRQ0 P63 P62 P61/CS5 P60/CS4 Pin functions in modes 1, 2, 3, and 7 P67 (I/O)/IRQ3 (input) P66 (I/O)/IRQ2 (input) P65 (I/O)/IRQ1 (input) P64 (I/O)/IRQ0 (input) P63 (I/O) P62 (I/O) P61 (I/O) P60 (I/O) Pin functions in modes 4 to 6 P67 (input)/IRQ3 (input)/CS7 (output) P66 (input)/IRQ2 (input)/CS6 (output) P65 (I/O)/IRQ1 (input) P64 (I/O)/IRQ0 (input) P63 (I/O) P62 (I/O) P61 (input)/CS5 (output) P60 (input)/CS4 (output)
Figure 8.6 Port 6 Pin Functions
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8. I/O Ports
8.7.2
Register Configuration
Table 8.11 shows the port 6 register configuration. Table 8.11 Port 6 Registers
Name Port 6 data direction register Port 6 data register Port 6 register Note: * Abbreviation P6DDR P6DR PORT6 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB5 H'FF65 H'FF55
Lower 16 bits of the address.
Port 6 Data Direction Register (P6DDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : R/W :
P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P6DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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Port 6 Data Register (P6DR)
Bit : 7 P67DR Initial value : R/W : 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W
P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). P6DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port 6 Register (PORT6)
Bit : 7 P67 Initial value : RW : --* R 6 P66 --* R 5 P65 --* R 4 P64 --* R 3 P63 --* R 2 P62 --* R 1 P61 --* R 0 P60 --* R
Note: * Determined by state of pins P67 to P60.
PORT6 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 6 pins (P67 to P60) must always be performed on P6DR. If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT6 contents are determined by the pin states, as P6DDR and P6DR are initialized. PORT6 retains its prior state after a manual reset, and in software standby mode.
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8.7.3
Pin Functions
Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3) and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 8.12. Table 8.12 Port 6 Pin Functions
Pin P67/IRQ3/CS7 Selection Method and Pin Functions The pin function is switched as shown below according to bit P67DDR. Mode P67DDR Pin function Modes 1, 2, 3, 7 0 P67 input pin 1 P67 output pin 0 P67 input pin Modes 4 to 6 1 CS7 output pin
IRQ3 interrupt input pin P66/IRQ2/CS6 The pin function is switched as shown below according to bit P66DDR. Mode P66DDR Pin function Modes 1, 2, 3, 7 0 P66 input pin 1 P66 output pin 0 P66 input pin Modes 4 to 6 1 CS6 output pin
IRQ2 interrupt input pin
P65/IRQ1
The pin function is switched as shown below according to bit P65DDR. P65DDR Pin function 0 P65 input pin IRQ1 interrupt input pin 1 P65 output pin
P64/IRQ0
The pin function is switched as shown below according to bit P64DDR. P64DDR Pin function 0 P64 input pin IRQ0 interrupt input pin 1 P64 output pin
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8. I/O Ports Pin P63 Selection Method and Pin Functions The pin function is switched as shown below according to bit P63DDR. P63DDR Pin function 0 P63 input pin 1 P63 output pin
P62
The pin function is switched as shown below according to bit P62DDR. P62DDR Pin function 0 P62 input pin 1 P62 output pin
P61/CS5
The pin function is switched as shown below according to bit P61DDR. Mode P61DDR Pin function Modes 1, 2, 3, 7 0 P61 input pin 1 P61 output pin 0 P61 input pin Modes 4 to 6 1 CS5 output pin
P60/CS4
The pin function is switched as shown below according to bit P60DDR. Mode P60DDR Pin function Modes 1, 2, 3, 7 0 P60 input pin 1 P60 output pin 0 P60 input pin Modes 4 to 6 1 CS4 output pin
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8. I/O Ports
8.8
8.8.1
Port A
Overview
Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Pins PA7 to PA4 are schmitt-triggered inputs. Figure 8.7 shows the port A pin configuration.
Port A pins PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 Port A PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 Pin functions in modes 1, 2, 3, and 7 PA7 (I/O)/IRQ7 (input) PA6 (I/O)/IRQ6 (input) PA5 (I/O)/IRQ5 (input) PA4 (I/O)/IRQ4 (input) PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O)
Pin functions in modes 4 and 5 PA7 (input)/A23 (output)/IRQ7 (input) PA6 (input)/A22 (output)/IRQ6 (input) PA5 (input)/A21 (output)/IRQ5 (input) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output)
Pin functions in mode 6 PA7 (input)/A23 (output)/IRQ7 (input) PA6 (input)/A22 (output)/IRQ6 (input) PA5 (input)/A21 (output)/IRQ5 (input) PA4 (input)/A20 (output)/IRQ4 (input) PA3 (input)/A19 (output) PA2 (input)/A18 (output) PA1 (input)/A17 (output) PA0 (input)/A16 (output)
Figure 8.7 Port A Pin Functions
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8. I/O Ports
8.8.2
Register Configuration
Table 8.13 shows the port A register configuration. Table 8.13 Port A Registers
Name Port A data direction register Port A data register Port A register Port A MOS pull-up control register Port A open-drain control register Note: * Abbreviation PADDR PADR PORTA PAPCR PAODR R/W W R/W R R/W R/W Initial Value H'00 H'00 Undefined H'00 H'00 Address * H'FEB9 H'FF69 H'FF59 H'FF70 H'FF77
Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit Initial value R/W : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 2, 3, and 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 4 and 5 The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to PA0DDR. Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port.
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* Mode 6 Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the pin an input port. Port A Data Register (PADR)
Bit : 7 PA7DR Initial value : R/W : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0). PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Register (PORTA)
Bit : 7 PA7 Initial value : R/W : --* R 6 PA6 --* R 5 PA5 --* R 4 PA4 --* R 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R 0 PA0 --* R
Note: * Determined by state of pins PA7 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA7 to PA0) must always be performed on PADR. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset, and in software standby mode.
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Port A MOS Pull-Up Control Register (PAPCR)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : R/W :
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. All the bits are valid in modes 1, 2, 3, 6, and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Open Drain Control Register (PAODR)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : R/W :
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA7 to PA0). All bits are valid in modes 1, 2, 3, and 7. Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8.8.3
Pin Functions
Modes 1, 2, 3 and 7: In mode 1, 2, 3, and 7, port A pins function as I/O ports and interrupt input pins. Input or output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A pin functions in modes 1, 2, 3, and 7 are shown in figure 8.8.
PA7 (I/O)/IRQ7 (input) PA6 (I/O)/IRQ6 (input) PA5 (I/O)/IRQ5 (input) Port A PA4 (I/O)/IRQ4 (input) PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O)
Figure 8.8 Port A Pin Functions (Modes 1, 2, 3, and 7) Modes 4 and 5: In modes 4 and 5, the lower 5 bits of port A are designated as address outputs automatically, while the upper 3 bits function as address outputs or input ports and interrupt input pins. Input or output can be specified individually for the upper 3 bits. Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port.
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Port A pin functions in modes 4 and 5 are shown in figure 8.9.
When PADDR = 1 A23 (output) A22 (output) A21 (output) Port A A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) When PADDR = 0 PA7 (input)/IRQ7 (input) PA6 (input)/IRQ6 (input) PA5 (input)/IRQ5 (input) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output)
Figure 8.9 Port A Pin Functions (Modes 4 and 5) Mode 6: In mode 6, port A pins function as address outputs or input ports and interrupt input pins. Input or output can be specified on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Port A pin functions in mode 6 are shown in figure 8.10.
When PADDR = 1 A23 (output) A22 (output) A21 (output) Port A A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) When PADDR = 0 PA7 (input)/IRQ7 (input) PA6 (input)/IRQ6 (input) PA5 (input)/IRQ5 (input) PA4 (input)/IRQ4 (input) PA3 (input) PA2 (input) PA1 (input) PA0 (input)
Figure 8.10 Port A Pin Functions (Mode 6)
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8. I/O Ports
8.8.4
MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA5 in modes 4 and 5, and by all pins in modes 1, 2, 3, 6, and 7. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 8.14 summarizes the MOS input pull-up states. Table 8.14 MOS Input Pull-Up States (Port A)
Modes 1 to 3, 6, 7 PA7 to PA0 4, 5 PA7 to PA5 PA4 to PA0 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode ON/OFF ON/OFF OFF In Other Operations
Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off.
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8.9
8.9.1
Port B
Overview
Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 8.11 shows the port B pin configuration.
Port B pins PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 Port B PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 Pin functions in modes 1, 4, and 5 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output)
Pin functions in modes 2 and 6 PB7 (input)/A15 (output) PB6 (input)/A14 (output) PB5 (input)/A13 (output) PB4 (input)/A12 (output) PB3 (input)/A11 (output) PB2 (input)/A10 (output) PB1 (input)/A9 (output) PB0 (input)/A8 (output)
Pin functions in modes 3 and 7 PB7 (I/O) PB6 (I/O) PB5 (I/O) PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O)
Figure 8.11 Port B Pin Functions
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8. I/O Ports
8.9.2
Register Configuration
Table 8.15 shows the port B register configuration. Table 8.15 Port B Registers
Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Note: * Abbreviation PBDDR PBDR PORTB PBPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBA H'FF6A H'FF5A H'FF71
Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W :
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits. * Modes 2 and 6 Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port.
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Port B Data Register (PBDR)
Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port B Register (PORTB)
Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R
Note: * Determined by state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and in software standby mode.
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Port B MOS Pull-Up Control Register (PBPCR)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W :
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When a PBDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8.9.3
Pin Functions
Modes 1, 4, and 5: In modes 1, 4, and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 1, 4, and 5 are shown in figure 8.12.
A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output)
Figure 8.12 Port B Pin Functions (Modes 1, 4, and 5) Modes 2 and 6: In modes 2 and 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. Port B pin functions in modes 2 and 6 are shown in figure 8.13.
When PBDDR = 1 A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When PBDDR = 0 PB7 (input) PB6 (input) PB5 (input) PB4 (input) PB3 (input) PB2 (input) PB1 (input) PB0 (input)
Figure 8.13 Port B Pin Functions (Modes 2 and 6)
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Modes 3 and 7: In modes 3 and 7, port B pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Port B pin functions in modes 3 and 7 are shown in figure 8.14.
PB7 (I/O) PB6 (I/O) PB5 (I/O) Port B PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O)
Figure 8.14 Port B Pin Functions (Modes 3 and 7)
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8.9.4
MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 8.16 summarizes the MOS input pull-up states. Table 8.16 MOS Input Pull-Up States (Port B)
Modes 1, 4, 5 2, 3, 6, 7 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode OFF ON/OFF In Other Operations
Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PBDDR = 0 and PBPCR = 1; otherwise off.
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8.10
8.10.1
Port C
Overview
Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 8.15 shows the port C pin configuration.
Port C pins PC7 / A7 PC6 / A6 PC5 / A5 Port C PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0
Pin functions in modes 1, 4, and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output)
Pin functions in modes 2 and 6 PC7 (input)/ A7 (output) PC6 (input)/ A6 (output) PC5 (input)/ A5 (output) PC4 (input)/ A4 (output) PC3 (input)/ A3 (output) PC2 (input)/ A2 (output) PC1 (input)/ A1 (output) PC0 (input)/ A0 (output)
Pin functions in modes 3 and 7 PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O)
Figure 8.15 Port C Pin Functions
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8.10.2
Register Configuration
Table 8.17 shows the port C register configuration. Table 8.17 Port C Registers
Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PCDDR PCDR PORTC PCPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBB H'FF6B H'FF5B H'FF72
Port C Data Direction Register (PCDDR)
Bit Initial value R/W : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits. * Modes 2 and 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port.
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Port C Data Register (PCDR)
Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port C Register (PORTC)
Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R
Note: * Determined by state of pins PC7 to PC0.
PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state after a manual reset, and in software standby mode.
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Port C MOS Pull-Up Control Register (PCPCR)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W :
PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When a PCDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.10.3 Pin Functions
Modes 1, 4, and 5: In modes 1, 4, and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 1, 4, and 5 are shown in figure 8.16.
A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output)
Figure 8.16 Port C Pin Functions (Modes 1, 4, and 5)
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Modes 2 and 6: In modes 2 and 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Port C pin functions in modes 2 and 6 are shown in figure 8.17.
When PCDDR = 1 A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input)
Figure 8.17 Port C Pin Functions (Modes 2 and 6) Modes 3 and 7: In modes 3 and 7, port C pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Port C pin functions in modes 3 and 7 are shown in figure 8.18.
PC7 (I/O) PC6 (I/O) PC5 (I/O) Port C PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O)
Figure 8.18 Port C Pin Functions (Modes 3 and 7)
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8.10.4
MOS Input Pull-Up Function
Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 8.18 summarizes the MOS input pull-up states. Table 8.18 MOS Input Pull-Up States (Port C)
Modes 1, 4, 5 2, 3, 6, 7 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode OFF ON/OFF In Other Operations
Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PCDDR = 0 and PCPCR = 1; otherwise off.
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8.11
8.11.1
Port D
Overview
Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 8.19 shows the port D pin configuration.
Port D pins PD7 /D15 PD6 /D14 PD5 /D13 Port D PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 Pin functions in modes 1, 2, 4, 5, and 6 D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Pin functions in modes 3 and 7 PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O)
Figure 8.19 Port D Pin Functions
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8.11.2
Register Configuration
Table 8.19 shows the port D register configuration. Table 8.19 Port D Registers
Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBC H'FF6C H'FF5C H'FF73
Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W :
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.. PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. * Modes 1, 2, 4, 5, and 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O. * Modes 3 and 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.
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Port D Data Register (PDDR)
Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port D Register (PORTD)
Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state after a manual reset, and in software standby mode.
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Port D MOS Pull-Up Control Register (PDPCR)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W :
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.11.3 Pin Functions
Modes 1, 2, 4, 5, and 6: In modes 1, 2, 4, 5, and 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8.20.
D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O)
Figure 8.20 Port D Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7: In modes 3 and 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.
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Port D pin functions in modes 3 and 7 are shown in figure 8.21.
PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O)
Figure 8.21 Port D Pin Functions (Modes 3 and 7) 8.11.4 MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 3 and 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 8.20 summarizes the MOS input pull-up states. Table 8.20 MOS Input Pull-Up States (Port D)
Modes 1, 2, 4 to 6 3, 7 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode OFF ON/OFF In Other Operations
Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PDDDR = 0 and PDPCR = 1; otherwise off.
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8.12
8.12.1
Port E
Overview
Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 8.22 shows the port E pin configuration.
Port E pins PE7 /D7 PE6 /D6 PE5 /D5 Port E PE4 /D4 PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 Pin functions in modes 1, 2, 4, 5, and 6 PE7 (I/O)/ D7 (I/O) PE6 (I/O)/ D6 (I/O) PE5 (I/O)/ D5 (I/O) PE4 (I/O)/ D4 (I/O) PE3 (I/O)/ D3 (I/O) PE2 (I/O)/ D2 (I/O) PE1 (I/O)/ D1 (I/O) PE0 (I/O)/ D0 (I/O) Pin functions in modes 3 and 7 PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O)
Figure 8.22 Port E Pin Functions
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8. I/O Ports
8.12.2
Register Configuration
Table 8.21 shows the port E register configuration. Table 8.21 Port E Registers
Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register Note: * Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBD H'FF6D H'FF5D H'FF74
Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W :
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. * Modes 1, 2, 4, 5, and 6 When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller. * Modes 3 and 7 Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
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Port E Data Register (PEDR)
Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port E Register (PORTE)
Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state after a manual reset, and in software standby mode. Port E MOS Pull-Up Control Register (PEPCR)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W :
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis.
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When a PEDDR bit is cleared to 0 (input port setting) when 8-bit bus mode is selected in mode 1, 2, 4, 5, or 6, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 8.12.3 Pin Functions
Modes 1, 2, 4, 5, and 6: In modes 1, 2, 4, 5, and 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Port E pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8.23.
8-bit bus mode PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) 16-bit bus mode D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O)
Figure 8.23 Port E Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7: In modes 3 and 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
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Port E pin functions in modes 3 and 7 are shown in figure 8.24.
PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O)
Figure 8.24 Port E Pin Functions (Modes 3 and 7) 8.12.4 MOS Input Pull-Up Function
Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2, 4, 5, and 6 when 8-bit bus mode is selected, or in mode 3 or 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 1, 2, 4, 5, or 6 when 8-bit bus mode is selected, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 8.22 summarizes the MOS input pull-up states. Table 8.22 MOS Input Pull-Up States (Port E)
Modes 3, 7 1, 2, 4 to 6 8-bit bus 16-bit bus OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PEDDR = 0 and PEPCR = 1; otherwise off. Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode ON/OFF In Other Operations
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8.13
8.13.1
Port F
Overview
Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, and BACK) and the system clock () output pin. Figure 8.25 shows the port F pin configuration.
Port F pins PF7/ PF6/AS PF5/RD Port F PF4/HWR PF3/LWR PF2/WAIT PF1/BACK PF0/BREQ Pin functions in modes 1, 2, 4, 5, and 6 PF7 (input)/ (output) AS (output) RD (output) HWR (output) LWR (output) PF2 (I/O)/WAIT (input) PF1 (I/O)/BACK (output) PF0 (I/O)/BREQ (input)
Pin functions in modes 3 and 7 PF7 (input)/ (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O) PF2 (I/O) PF1 (I/O) PF0 (I/O)
Figure 8.25 Port F Pin Functions
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8. I/O Ports
8.13.2
Register Configuration
Table 8.23 shows the port F register configuration. Table 8.23 Port F Registers
Name Port F data direction register Port F data register Port F register Abbreviation PFDDR PFDR PORTF R/W W R/W R Initial Value H'80/H'00* H'00 Undefined
2
Address* H'FEBE H'FF6E H'FF5E
1
Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit : 7 6 5 4 3 2 1 0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4, 5, 6 Initial value : R/W : Modes 3 and 7 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2, 4, 5, and 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 2, 4, 5, and 6 Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are automatically designated as bus control outputs (AS, RD, HWR, and LWR).
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8. I/O Ports
Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in the case of pin PF7, the output pin. Clearing the bit to 0 makes the pin an input port. Port F Data Register (PFDR)
Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port F Register (PORTF)
Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 PF0 --* R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
8.13.3
Pin Functions
Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, and BACK) and the system clock () output pin. The pin functions differ between modes 1, 2, 4, 5, and 6, and modes 3 and 7. Port F pin functions are shown in table 8.24. Table 8.24 Port F Pin Functions
Pin PF7/ Selection Method and Pin Functions The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 PF7 input pin 1 output pin
PF6/AS
The pin function is switched as shown below according to the operating mode and bit PF6DDR. Operating Mode PF6DDR Pin function Modes 1, 2, 4 to 6 -- AS output pin 0 PF6 input pin Modes 3 and 7 1 PF6 output pin
PF5/RD
The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode PF5DDR Pin function Modes 1, 2, 4 to 6 -- RD output pin 0 PF5 input pin Modes 3 and 7 1 PF5 output pin
PF4/HWR
The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode PF4DDR Pin function Modes 1, 2, 4 to 6 -- HWR output pin 0 PF4 input pin Modes 3 and 7 1 PF4 output pin
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8. I/O Ports Pin PF3/LWR Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PF3DDR. Operating Mode PF3DDR Pin function PF2/WAIT Modes 1, 2, 4 to 6 -- LWR output pin 0 PF3 input pin Modes 3 and 7 1 PF3 output pin
The pin function is switched as shown below according to the combination of the operating mode, and bits WAITE and PF2DDR. Operating Mode WAITE PF2DDR Pin function 0 PF2 input pin Modes 1, 2, 4 to 6 0 1 PF2 output pin 1 -- WAIT input pin 0 PF2 input pin Modes 3 and 7 -- 1 PF2 output pin
Note: PF1/BACK
*
Only when RMTS2 to RMTS0 = B'001 to B'011 and CW2 = 0 in modes 4 to 6.
The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF1DDR. Operating Mode BRLE PF1DDR Pin function 0 PF1 input pin Modes 1, 2, 4 to 6 0 1 PF1 output pin 1 -- BACK output pin 0 PF1 input pin Modes 3 and 7 -- 1 PF1 output pin
PF0/BREQ
The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode BRLE PF0DDR Pin function 0 PF0 input pin Modes 1, 2, 4 to 6 0 1 PF0 output pin 1 -- BREQ input pin 0 PF0 input pin Modes 3 and 7 -- 1 PF0 output pin
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8. I/O Ports
8.14
8.14.1
Port G
Overview
Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3). Figure 8.26 shows the port G pin configuration.
Port G pins Pin functions in modes 1 and 2
PG4/CS0 PG3/CS1 Port G PG2/CS2 PG1/CS3 PG0
PG4 (input)/CS0 (output) PG3 (I/O) PG2 (I/O) PG1 (I/O) PG0 (I/O)
Pin functions in modes 3 and 7
Pin functions in modes 4 to 6
PG4 (I/O) PG3 (I/O) PG2 (I/O) PG1 (I/O) PG0 (I/O)
PG4 (input)/CS0 (output) PG3 (input)/CS1 (output) PG2 (input)/CS2 (output) PG1 (input)/CS3 (output) PG0 (I/O)
Figure 8.26 Port G Pin Functions
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8. I/O Ports
8.14.2
Register Configuration
Table 8.25 shows the port G register configuration. Table 8.25 Port G Registers
Name Port G data direction register Port G data register Port G register Abbreviation PGDDR PGDR PORTG R/W W R/W R Initial Value* H'10/H'00* H'00 Undefined
3 2
Address* H'FEBF H'FF6F H'FF5F
1
Notes: 1. Lower 16 bits of the address. 2. Value of bits 4 to 0. 3. Initial value depends on the mode.
Port G Data Direction Register (PGDDR)
Bit : 7 -- Modes 1, 4, 5 Initial value : R/W : Modes 2, 3, 6, 7 Initial value : R/W : Undefined Undefined Undefined -- -- -- 0 W 0 W 0 W 0 W 0 W Undefined Undefined Undefined -- -- -- 1 W 0 W 0 W 0 W 0 W 6 -- 5 -- 4 3 2 1 0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read. The PGDDR4 bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes 1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. It retains its prior state after a manual reset and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode.
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8. I/O Ports
* Modes 1 and 2 Pin PG4 functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set to 1, and as an input port when the bit is cleared to 0. For pins PG3 to PG0, setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 4, 5, and 6 Pins PG4 to PG1 function as bus control output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0. Port G Data Register (PGDR)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
PG4DR PG3DR PG2DR
PG1DR PG0DR
Undefined Undefined Undefined
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
Port G Register (PORTG)
Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 PG4 --* R 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R 0 PG0 --* R
Undefined Undefined Undefined
Note: * Determined by state of pins PG4 to PG0.
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset, and in software standby mode.
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8. I/O Ports
8.14.3
Pin Functions
Port G pins also function as bus control signal output pins (CS0 to CS3). The pin functions are different in modes 1 and 2, modes 3 and 7, and modes 4 to 6. Port G pin functions are shown in table 8.26. Table 8.26 Port G Pin Functions
Pin PG4/CS0 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating Mode PG4DDR Pin function Modes 1, 2, 4 to 6 0 PG4 input pin 1 CS0 output pin Modes 3 and 7 0 1
PG4 input pin PG4 output pin
PG3/CS1
The pin function is switched as shown below according to the operating mode and bit PG3DDR. Operating Mode PG3DDR Pin function Modes 1, 2, 3, 7 0 1 0 Modes 4 to 6 1 CS1 output pin
PG3 input pin PG3 output pin PG3 input pin
PG2/CS2
The pin function is switched as shown below according to the operating mode and bit PG2DDR. Operating Mode PG2DDR Pin function Modes 1, 2, 3, 7 0 1 0 Modes 4 to 6 1 CS2 output pin
PG2 input pin PG2 output pin PG2 input pin
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8. I/O Ports Pin PG1/CS3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PG1DDR. Operating Mode PG1DDR Pin function Modes 1, 2, 3, 7 0 1 0 Modes 4 to 6 1 CS3 output pin
PG1 input pin PG1 output pin PG1 input pin
PG0
The pin function is switched as shown below according to the bit PG0DDR. PG0DDR Pin function 0 PG0 input pin 1 PG0 output pin
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9. 16-Bit Timer Pulse Unit (TPU)
Section 9 16-Bit Timer Pulse Unit (TPU)
9.1 Overview
The H8S/2355 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 9.1.1 Features
* Maximum 16-pulse input/output A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register TGRC and TGRD for channels 0 and 3 can also be used as buffer registers * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 Input capture register double-buffering possible Automatic rewriting of output compare register possible * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 Two-phase encoder pulse up/down-count possible * Cascaded operation Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow * Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface
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9. 16-Bit Timer Pulse Unit (TPU)
* 26 interrupt sources For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently * Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) activation * A/D converter conversion start trigger can be generated Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger * Module stop mode can be set As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode.
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9. 16-Bit Timer Pulse Unit (TPU)
Table 9.1 lists the functions of the TPU. Table 9.1
Item Count clock
TPU Functions
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGR1A TGR1B -- TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGR2A TGR2B -- TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGR3A TGR3B TGR3C TGR3D TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGR4A TGR4B -- TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGR5A TGR5B -- TIOCA5 TIOCB5
General registers General registers/ buffer registers I/O pins
Counter clear function
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation -- -- -- -- -- --
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9. 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 TGR compare match or input capture TGR1A compare match or input capture Channel 2 TGR compare match or input capture TGR2A compare match or input capture Channel 3 TGR compare match or input capture TGR3A compare match or input capture 5 sources Channel 4 TGR compare match or input capture TGR4A compare match or input capture 4 sources Channel 5 TGR compare match or input capture TGR5A compare match or input capture 4 sources
DTC TGR activation compare match or input capture A/D TGR0A converter compare trigger match or input capture Interrupt sources
5 sources 4 sources 4 sources * Compare * Compare * Compare match or match or match or input input capture input capture 0A 1A capture 2A * Compare * Compare * Compare match or match or match or input input input capture 0B capture 1B capture 2B * Compare * Overflow * Overflow match or * Underflow * Underflow input capture 0C * Compare match or input capture 0D * Overflow
* Compare * Compare * Compare match or match or match or input input input capture 3A capture 4A capture 5A * Compare * Compare * Compare match or match or match or input input input capture 3B capture 4B capture 5B * Compare * Overflow match or * Underflow input capture 3C * Compare match or input capture 3D * Overflow * Overflow * Underflow
Legend: : Possible -- : Not possible
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9. 16-Bit Timer Pulse Unit (TPU)
9.1.2
Block Diagram
Figure 9.1 shows a block diagram of the TPU.
TIORH TIORL
TMDR
Channel 3
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Control logic for channels 3 to 5
Input/output pins Channel 3: TIOCA3 TIOCB3 TIOCC3 TIOCD3 Channel 4: TIOCA4 TIOCB4 TIOCA5 Channel 5: TIOCB5
Channel 5
TIOR
TMDR
Channel 2
TSR
Clock input Internal clock: /1 /4 /16 /64 /256 /1024 /4096 External clock: TCLKA TCLKB TCLKC TCLKD
TIER
TCR
Module data bus
TSTR TSYR
TGRA
Bus interface
TGRB
TCNT
Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U
TMDR
Channel 4
TSR
TIER
TCR
TGRA
TIOR
TMDR
TSR
TIER
TCR
TGRB
TCNT
Common
Control logic
Internal data bus
A/D conversion start request signal
TIOR
TIER
TCR
TGRA
TGRB
TCNT
Control logic for channels 0 to 2
TIORH TIORL
TMDR
Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2
Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U
TMDR
Channel 1
TSR
TIOR
Channel 0
TSR
TIER
TCR
TGRA
TGRB TGRD TGRC TGRB
TCNT TCNT
Figure 9.1 Block Diagram of TPU
TIER
TCR
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TGRA
9. 16-Bit Timer Pulse Unit (TPU)
9.1.3
Pin Configuration
Table 9.2 summarizes the TPU pins. Table 9.2
Channel All
TPU Pins
Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin
Clock input B
TCLKB
Input
Clock input C
TCLKC
Input
Clock input D
TCLKD
Input
0
Input capture/out TIOCA0 compare match A0 Input capture/out TIOCB0 compare match B0 Input capture/out TIOCC0 compare match C0 Input capture/out TIOCD0 compare match D0
I/O I/O I/O I/O I/O I/O I/O I/O
1
Input capture/out TIOCA1 compare match A1 Input capture/out TIOCB1 compare match B1
2
Input capture/out TIOCA2 compare match A2 Input capture/out TIOCB2 compare match B2
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9. 16-Bit Timer Pulse Unit (TPU) Channel 3 Name Symbol I/O I/O I/O I/O I/O I/O I/O I/O I/O Function TGR3A input capture input/output compare output/PWM output pin TGR3B input capture input/output compare output/PWM output pin TGR3C input capture input/output compare output/PWM output pin TGR3D input capture input/output compare output/PWM output pin TGR4A input capture input/output compare output/PWM output pin TGR4B input capture input/output compare output/PWM output pin TGR5A input capture input/output compare output/PWM output pin TGR5B input capture input/output compare output/PWM output pin
Input capture/out TIOCA3 compare match A3 Input capture/out TIOCB3 compare match B3 Input capture/out TIOCC3 compare match C3 Input capture/out TIOCD3 compare match D3
4
Input capture/out TIOCA4 compare match A4 Input capture/out TIOCB4 compare match B4
5
Input capture/out TIOCA5 compare match A5 Input capture/out TIOCB5 compare match B5
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9. 16-Bit Timer Pulse Unit (TPU)
9.1.4
Register Configuration
Table 9.3 summarizes the TPU registers. Table 9.3 TPU Registers
Abbreviation TCR0 TMDR0 TIOR0H TIOR0L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W
2 2
Channel Name 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L
Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40
Address* H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA
1
Timer interrupt enable register 0 TIER0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1
Timer interrupt enable register 1 TIER1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2
R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W
2
H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40
Timer interrupt enable register 2 TIER2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B TSR2 TCNT2 TGR2A TGR2B
R/(W) * H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF
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9. 16-Bit Timer Pulse Unit (TPU) Channel Name 3 Timer control register 3 Timer mode register 3 Timer I/O control register 3H Timer I/O control register 3L Abbreviation TCR3 TMDR3 TIOR3H TIOR3L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W
2 2
Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40
Address* H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FFC0 H'FFC1 H'FF3C
1
Timer interrupt enable register 3 TIER3 Timer status register 3 Timer counter 3 Timer general register 3A Timer general register 3B Timer general register 3C Timer general register 3D 4 Timer control register 4 Timer mode register 4 Timer I/O control register 4 TSR3 TCNT3 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4
Timer interrupt enable register 4 TIER4 Timer status register 4 Timer counter 4 Timer general register 4A Timer general register 4B 5 Timer control register 5 Timer mode register 5 Timer I/O control register 5 TSR4 TCNT4 TGR4A TGR4B TCR5 TMDR5 TIOR5
R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W
2
H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40
Timer interrupt enable register 5 TIER5 Timer status register 5 Timer counter 5 Timer general register 5A Timer general register 5B All Timer start register Timer synchro register Module stop control register TSR5 TCNT5 TGR5A TGR5B TSTR TSYR MSTPCR
R/(W) * H'C0 R/W R/W R/W R/W R/W R/W H'0000 H'FFFF H'FFFF H'00 H'00 H'3FFF
Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.
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9. 16-Bit Timer Pulse Unit (TPU)
9.2
9.2.1
Register Descriptions
Timer Control Register (TCR)
Channel 0: TCR0 Channel 3: TCR3
Bit
:
7 CCLR2 0 R/W
6 CCLR1 0 R/W
5 CCLR0 0 R/W
4 0 R/W
3 0 R/W
2 TPSC2 0 R/W
1 TPSC1 0 R/W
0 TPSC0 0 R/W
CKEG1 CKEG0
Initial value : R/W :
Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5
Bit
:
7 -- 0 --
6 CCLR1 0 R/W
5 CCLR0 0 R/W
4 0 R/W
3 0 R/W
2 TPSC2 0 R/W
1 TPSC1 0 R/W
0 TPSC0 0 R/W
CKEG1 CKEG0
Initial value : R/W :
The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. TCR register settings should be made only when TCNT operation is stopped.
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9. 16-Bit Timer Pulse Unit (TPU)
Bits 7, 6, 5--Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source.
Bit 7 Channel 0, 3 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value)
TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation * TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture * TCNT cleared by TGRD compare match/input 2 capture * TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation *
1
0
0 1
1
0 1
Bit 7 Channel 1, 2, 4, 5
3
Bit 6
Bit 5 CCLR0 0 1 Description TCNT clearing disabled (Initial value)
Reserved* CCLR1 0 0
TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation *
1
0 1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.
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9. 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 -- Description Count at rising edge Count at falling edge Count at both edges (Initial value)
Note: Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected.
Bits 2, 1, and 0--Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 9.4 shows the clock sources that can be set for each channel. Table 9.4 TPU Clock Sources
Overflow/ Underflow External Clock on Another TCLKA TCLKB TCLKC TCLKD Channel
Internal Clock Channel 0 1 2 3 4 5 /1 /4 /16 /64 /256 /1024 /4096
Legend: : Setting Blank : No setting
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9. 16-Bit Timer Pulse Unit (TPU) Bit 2 Channel 0 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input (Initial value)
Bit 2 Channel 1 TPSC2 0
Bit 1 TPSC1 0
Bit 0 TPSC0 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow (Initial value)
1
0 1
1
0
0 1
1
0 1
Note: This setting is ignored when channel 1 is in phase counting mode.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 2 Channel 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 (Initial value)
Note: This setting is ignored when channel 2 is in phase counting mode. Bit 2 Channel 3 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096 (Initial value)
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9. 16-Bit Timer Pulse Unit (TPU) Bit 2 Channel 4 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow (Initial value)
Note: This setting is ignored when channel 4 is in phase counting mode. Bit 2 Channel 5 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input (Initial value)
Note: This setting is ignored when channel 5 is in phase counting mode.
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.2
Timer Mode Register (TMDR)
Channel 0: TMDR0 Channel 3: TMDR3
Bit
:
7 -- 1 --
6 -- 1 --
5 BFB 0 R/W
4 BFA 0 R/W
3 MD3 0 R/W
2 MD2 0 R/W
1 MD1 0 R/W
0 MD0 0 R/W
Initial value : R/W :
Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5
Bit
:
7 -- 1 --
6 -- 1 --
5 -- 0 --
4 -- 0 --
3 MD3 0 R/W
2 MD2 0 R/W
1 MD1 0 R/W
0 MD0 0 R/W
Initial value : R/W :
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6--Reserved: Read-only bits, always read as 1. Bit 5--Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation (Initial value)
Bit 4--Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.
Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value)
Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3 MD3*1 0 Bit 2 MD2*2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- (Initial value)
Legend: *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.3
Timer I/O Control Register (TIOR)
Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5
Bit
:
7 IOB3 0 R/W
6 IOB2 0 R/W
5 IOB1 0 R/W
4 IOB0 0 R/W
3 IOA3 0 R/W
2 IOA2 0 R/W
1 IOA1 0 R/W
0 IOA0 0 R/W
Initial value : R/W :
Channel 0: TIOR0L Channel 3: TIOR3L Bit :
7 IOD3 0 R/W
6 IOD2 0 R/W
5 IOD1 0 R/W
4 IOD0 0 R/W
3 IOC3 0 R/W
2 IOC2 0 R/W
1 IOC1 0 R/W
0 IOC0 0 R/W
Initial value : R/W :
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
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9. 16-Bit Timer Pulse Unit (TPU)
Bits 7 to 4-- I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD.
Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0B is Capture input input source is TIOCB0 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 1 source is channel count- up/count-down* 1/count clock
Legend: *: Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 0 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is Capture input input source is capture TIOCD0 pin 2 register* Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0D is Output disabled output Initial output is 0 compare output 2 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 1 source is channel count-up/count-down* 1/count clock
Legend: *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 1 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is Capture input source is input TIOCB1 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at generation source is TGR0C of TGR0C compare compare match/ match/input capture input capture
Legend: *: Don't care
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 2 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 Legend: *: Don't care * TGR2B is Capture input input source is capture TIOCB2 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 3 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is Capture input source is input capture TIOCB3 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT4 1 source is channel count-up/count-down* 4/count clock
Legend: *: Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 3 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR3D is Capture input source is input TIOCD3 pin capture 2 register* Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 1 count-up/count-down* TGR3D is Output disabled output Initial output is 0 compare output 2 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR4B is Capture input source is input TIOCB4 pin capture register Capture input source is TGR3C compare match/ input capture Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of TGR3C compare match/ input capture TGR4B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don't care
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9. 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel 5 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 Legend: *: Don't care * TGR5B is Capture input input source is capture TIOCB5 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR5B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
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9. 16-Bit Timer Pulse Unit (TPU)
Bits 3 to 0-- I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC.
Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0A is Capture input input source is capture TIOCA0 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 source is channel count-up/count-down 1/ count clock
Legend: *: Don't care
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is Capture input source is input capture TIOCC0 pin 1 register* Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0C is Output disabled output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 source is channel count-up/count-down 1/count clock
Legend: *: Don't care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 1 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is Capture input source is input capture TIOCA1 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at generation source is TGR0A of channel 0/TGR0A compare match/ compare match/input capture input capture
Legend: *: Don't care
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 2 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 Legend: *: Don't care * TGR2A is Capture input input source is capture TIOCA2 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 3 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is Capture input source is input TIOCA3 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock
Legend: *: Don't care
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 3 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3C is Capture input source is input capture TIOCC3 pin 1 register* Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3C is Output disabled output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock
Legend: *: Don't care Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 4 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is Capture input source is input TIOCA4 pin capture register Capture input source is TGR3A compare match/ input capture Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of TGR3A compare match/input capture TGR4A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Legend: *: Don't care
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9. 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel 5 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 Legend: *: Don't care * TGR5A is Capture input input source is capture TIOCA5 pin register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR5A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.4
Timer Interrupt Enable Register (TIER)
Channel 0: TIER0 Channel 3: TIER3
Bit
:
7 TTGE 0 R/W
6 -- 1 --
5 -- 0 --
4 TCIEV 0 R/W
3 TGIED 0 R/W
2 TGIEC 0 R/W
1 TGIEB 0 R/W
0 TGIEA 0 R/W
Initial value : R/W :
Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5
Bit
:
7 TTGE 0 R/W
6 -- 1 --
5 TCIEU 0 R/W
4 TCIEV 0 R/W
3 -- 0 --
2 -- 0 --
1 TGIEB 0 R/W
0 TGIEA 0 R/W
Initial value : R/W :
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode.
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9. 16-Bit Timer Pulse Unit (TPU)
Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Bit 7 TTGE 0 1 Description A/D conversion start request generation disabled A/D conversion start request generation enabled (Initial value)
Bit 6--Reserved: Read-only bit, always read as 1. Bit 5--Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5 TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value)
Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1.
Bit 4 TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value)
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9. 16-Bit Timer Pulse Unit (TPU)
Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3 TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value)
Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2 TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value)
Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1 TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value)
Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0 TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value)
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.5
Timer Status Register (TSR)
Channel 0: TSR0 Channel 3: TSR3
Bit
:
7 -- 1 --
6 -- 1 --
5 -- 0 --
4 TCFV 0 R/(W)*
3 TGFD 0 R/(W)*
2 TGFC 0 R/(W)*
1 TGFB 0 R/(W)*
0 TGFA 0 R/(W)*
Initial value : R/W :
Note: * Can only be written with 0 for flag clearing.
Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5
Bit
:
7 TCFD 1 R
6 -- 1 --
5 TCFU 0 R/(W)*
4 TCFV 0 R/(W)*
3 -- 0 --
2 -- 0 --
1 TGFB 0 R/(W)*
0 TGFA 0 R/(W)*
Initial value : R/W :
Note: * Can only be written with 0 for flag clearing.
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. Bit 7--Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value)
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9. 16-Bit Timer Pulse Unit (TPU)
Bit 6--Reserved: Read-only bit, always read as 1. Bit 5--Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5 TCFU 0 1 Description [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) (Initial value)
Bit 4--Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.
Bit 4 TCFV 0 1 Description [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) (Initial value)
Bit 3--Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3 TGFD 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFD after reading TGFD = 1 When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register (Initial value)
When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
[Setting conditions]
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9. 16-Bit Timer Pulse Unit (TPU)
Bit 2--Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2 TGFC 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFC after reading TGFC = 1 When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register (Initial value)
When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
[Setting conditions]
Bit 1--Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match.
Bit 1 TGFB 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFB after reading TGFB = 1 When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register (Initial value)
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
[Setting conditions]
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9. 16-Bit Timer Pulse Unit (TPU)
Bit 0--Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match.
Bit 0 TGFA 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFA after reading TGFA = 1 When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register (Initial value)
When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
[Setting conditions]
9.2.6
Timer Counter (TCNT)
Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note : * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters.
The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.7
Bit
Timer General Register (TGR)
: 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD.
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.8
Bit
Timer Start Register (TSTR)
: 7 -- 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
Initial value : R/W :
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT.
Bit n CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value)
n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.9
Bit
Timer Synchro Register (TSYR)
: 7 -- 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
Initial value : R/W :
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels* , and 2 synchronous clearing through counter clearing on another channel* are possible.
Bit n SYNCn 0 1 Description TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0 Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR.
1
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9. 16-Bit Timer Pulse Unit (TPU)
9.2.10
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 13--Module Stop (MSTP13): Specifies the TPU module stop mode.
Bit 13 MSTP13 0 1 Description TPU module stop mode cleared TPU module stop mode set (Initial value)
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9. 16-Bit Timer Pulse Unit (TPU)
9.3
9.3.1
Interface to Bus Master
16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 9.2.
Internal data bus H Bus master Module data bus
L
Bus interface
TCNTH
TCNTL
Figure 9.2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 9.3.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 9.3, 9.4, and 9.5.
Internal data bus H Bus master Module data bus
L
Bus interface
TCR
Figure 9.3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)]
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9. 16-Bit Timer Pulse Unit (TPU)
Internal data bus H Bus master Module data bus
L
Bus interface
TMDR
Figure 9.4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)]
Internal data bus H Bus master Module data bus
L
Bus interface
TCR
TMDR
Figure 9.5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)]
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9. 16-Bit Timer Pulse Unit (TPU)
9.4
9.4.1
Operation
Overview
Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. * When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4 counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32bit counter. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input.
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9. 16-Bit Timer Pulse Unit (TPU)
9.4.2
Basic Functions
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. * Example of count operation setting procedure Figure 9.6 shows an example of the count operation setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation [5] [5] Set the CST bit in TSTR to 1 to start the counter operation.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count operation
[5]
Figure 9.6 Example of Counter Operation Setting Procedure
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9. 16-Bit Timer Pulse Unit (TPU)
* Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 9.7 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 9.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000.
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9. 16-Bit Timer Pulse Unit (TPU)
Figure 9.8 illustrates periodic counter operation.
TCNT value TGR Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software or DTC activation TGF
Figure 9.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. * Example of setting procedure for waveform output by compare match Figure 9.9 shows an example of the setting procedure for waveform output by compare match
[1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR.
Set output timing [2]
Output selection
Select waveform output mode
[1]
[3] Set the CST bit in TSTR to 1 to start the count operation.
Start count operation
[3]

Figure 9.9 Example of Setting Procedure for Waveform Output by Compare Match
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9. 16-Bit Timer Pulse Unit (TPU)
* Examples of waveform output operation Figure 9.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time
Figure 9.10 Example of 0 Output/1 Output Operation Figure 9.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output
TIOCB TIOCA
Figure 9.11 Example of Toggle Output Operation
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9. 16-Bit Timer Pulse Unit (TPU)
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. * Example of input capture operation setting procedure Figure 9.12 shows an example of the input capture operation setting procedure.
[1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge.
[1]
Input selection
Select input capture input
[2] Set the CST bit in TSTR to 1 to start the count operation.
Start count
[2]

Figure 9.12 Example of Input Capture Operation Setting Procedure
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9. 16-Bit Timer Pulse Unit (TPU)
* Example of input capture operation Figure 9.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 9.13 Example of Input Capture Operation
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9. 16-Bit Timer Pulse Unit (TPU)
9.4.3
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 9.14 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation [1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing sourcegeneration channel? Yes Select counter clearing source Start count
No
[3] [5]
Set synchronous counter clearing Start count
[4] [5]

[1] [2] [3] [4] [5]

Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 9.14 Example of Synchronous Operation Setting Procedure
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9. 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 9.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 9.4.6, PWM Modes.
Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time
TIOC0A TIOC1A TIOC2A
Figure 9.15 Example of Synchronous Operation
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9. 16-Bit Timer Pulse Unit (TPU)
9.4.4
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 9.5 shows the register combinations used in buffer operation. Table 9.5
Channel 0
Register Combinations in Buffer Operation
Timer General Register TGR0A TGR0B Buffer Register TGR0C TGR0D TGR3C TGR3D
3
TGR3A TGR3B
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.16.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 9.16 Compare Match Buffer Operation
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9. 16-Bit Timer Pulse Unit (TPU)
* When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9.17.
Input capture signal Timer general register
Buffer register
TCNT
Figure 9.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 9.18 shows an example of the buffer operation setting procedure.
[1] Designate TGR as an input capture register or output compare register by means of TIOR.
[1]
Buffer operation
Select TGR function
[2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Set buffer operation
[2]
Start count
[3]

Figure 9.18 Example of Buffer Operation Setting Procedure
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9. 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation * When TGR is an output compare register Figure 9.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 9.4.6, PWM Modes.
TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520
H'0450
TIOCA
Figure 9.19 Example of Buffer Operation (1)
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9. 16-Bit Timer Pulse Unit (TPU)
* When TGR is an input capture register Figure 9.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 9.20 Example of Buffer Operation (2)
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9. 16-Bit Timer Pulse Unit (TPU)
9.4.5
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.6 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 9.6 Cascaded Combinations
Upper 16 Bits TCNT1 TCNT4 Lower 16 Bits TCNT2 TCNT5
Combination Channels 1 and 2 Channels 4 and 5
Example of Cascaded Operation Setting Procedure: Figure 9.21 shows an example of the setting procedure for cascaded operation.
[1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'111 to select TCNT2 (TCNT5) overflow/underflow counting.
[1]
Cascaded operation
Set cascading
[2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Start count
[2]

Figure 9.21 Cascaded Operation Setting Procedure
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9. 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation: Figure 9.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
TCNT1 clock TCNT1 TCNT2 clock TCNT2 TIOCA1, TIOCA2 TGR1A H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2
TGR2A
H'0000
Figure 9.22 Example of Cascaded Operation (1) Figure 9.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, and phase counting mode has been designated for channel 2. TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
TCLKA
TCLKB TCNT2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF
TCNT1
0000
0001
0000
Figure 9.23 Example of Cascaded Operation (2)
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9. 16-Bit Timer Pulse Unit (TPU)
9.4.6
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 9.7.
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9. 16-Bit Timer Pulse Unit (TPU)
Table 9.7
PWM Output Registers and Output Pins
Output Pins
Channel 0
Registers TGR0A TGR0B TGR0C TGR0D
PWM Mode 1 TIOCA0
PWM Mode 2 TIOCA0 TIOCB0
TIOCC0
TIOCC0 TIOCD0
1
TGR1A TGR1B
TIOCA1
TIOCA1 TIOCB1
2
TGR2A TGR2B
TIOCA2
TIOCA2 TIOCB2
3
TGR3A TGR3B TGR3C TGR3D
TIOCA3
TIOCA3 TIOCB3
TIOCC3
TIOCC3 TIOCD3
4
TGR4A TGR4B
TIOCA4
TIOCA4 TIOCB4
5
TGR5A TGR5B
TIOCA5
TIOCA5 TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
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9. 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 9.24 shows an example of the PWM mode setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
Select counter clearing source [2]
PWM mode
Select counter clock
[1]
Select waveform output level
[3]
[3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR.
Set TGR
[4]
Set PWM mode
[5]
[6] Set the CST bit in TSTR to 1 to start the count operation.
Start count
[6]

Figure 9.24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 9.25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty.
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9. 16-Bit Timer Pulse Unit (TPU)
TCNT value TGRA
Counter cleared by TGRA compare match
TGRB H'0000 Time
TIOCA
Figure 9.25 Example of PWM Mode Operation (1) Figure 9.26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty.
Counter cleared by TGR1B compare match
TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000
Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1
Figure 9.26 Example of PWM Mode Operation (2)
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9. 16-Bit Timer Pulse Unit (TPU)
Figure 9.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT value TGRA TGRB rewritten
TGRB H'0000 0% duty
TGRB rewritten
TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty
TGRB rewritten Time
TIOCA
Figure 9.27 Example of PWM Mode Operation (3)
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9. 16-Bit Timer Pulse Unit (TPU)
9.4.7
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 9.8 shows the correspondence between external clock pins and channels. Table 9.8 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 9.28 shows an example of the phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]

Figure 9.28 Example of Phase Counting Mode Setting Procedure
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9. 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 9.29 shows an example of phase counting mode 1 operation, and table 9.9 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count
Time
Figure 9.29 Example of Phase Counting Mode 1 Operation Table 9.9 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level
Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count
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9. 16-Bit Timer Pulse Unit (TPU)
* Phase counting mode 2 Figure 9.30 shows an example of phase counting mode 2 operation, and table 9.10 summarizes the TCNT up/down-count conditions.
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count
Time
Figure 9.30 Example of Phase Counting Mode 2 Operation Table 9.10 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count Up-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care
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9. 16-Bit Timer Pulse Unit (TPU)
* Phase counting mode 3 Figure 9.31 shows an example of phase counting mode 3 operation, and table 9.11 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 9.31 Example of Phase Counting Mode 3 Operation Table 9.11 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Up-count Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care
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9. 16-Bit Timer Pulse Unit (TPU)
* Phase counting mode 4 Figure 9.32 shows an example of phase counting mode 4 operation, and table 9.12 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count
Up-count
Time
Figure 9.32 Example of Phase Counting Mode 4 Operation Table 9.12 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
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9. 16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode Application Example: Figure 9.33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved.
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9. 16-Bit Timer Pulse Unit (TPU)
Channel 1 TCLKA TCLKB Edge detection circuit TCNT1
TGR1A (speed period capture) TGR1B (position period capture)
TCNT0
+
TGR0A (speed control period)
-
TGR0C (position control period)
+ -
TGR0B (pulse width capture)
TGR0D (buffer operation) Channel 0
Figure 9.33 Phase Counting Mode Application Example
9.5
9.5.1
Interrupts
Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller.
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Table 9.13 lists the TPU interrupt sources. Table 9.13 TPU Interrupt Sources
Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Description TGR0A input capture/compare match TGR0B input capture/compare match TGR0C input capture/compare match TGR0D input capture/compare match TCNT0 overflow TGR1A input capture/compare match TGR1B input capture/compare match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare match TGR2B input capture/compare match TCNT2 overflow TCNT2 underflow TGR3A input capture/compare match TGR3B input capture/compare match TGR3C input capture/compare match TGR3D input capture/compare match TCNT3 overflow TGR4A input capture/compare match TGR4B input capture/compare match TCNT4 overflow TCNT4 underflow TGR5A input capture/compare match TGR5B input capture/compare match TCNT5 overflow TCNT5 underflow DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Low Priority High
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
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9. 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four overflow interrupts, one each for channels 1, 2, 4, and 5. 9.5.2 DTC Activation
DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, Data Transfer Controller. A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 9.5.3 A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.
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9. 16-Bit Timer Pulse Unit (TPU)
9.6
9.6.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Figure 9.34 shows TCNT count timing in internal clock operation, and figure 9.35 shows TCNT count timing in external clock operation.
Internal clock
Falling edge
Rising edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 9.34 Count Timing in Internal Clock Operation
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 9.35 Count Timing in External Clock Operation
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Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.36 shows output compare output timing.
TCNT input clock TCNT N N+1
TGR
N
Compare match signal TIOC pin
Figure 9.36 Output Compare Output Timing Input Capture Signal Timing: Figure 9.37 shows input capture signal timing.
Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 9.37 Input Capture Input Signal Timing
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Timing for Counter Clearing by Compare Match/Input Capture: Figure 9.38 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.39 shows the timing when counter clearing by input capture occurrence is specified.
Compare match signal Counter clear signal N H'0000
TCNT
TGR
N
Figure 9.38 Counter Clear Timing (Compare Match)
Input capture signal
Counter clear signal N H'0000
TCNT
TGR
N
Figure 9.39 Counter Clear Timing (Input Capture)
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Buffer Operation Timing: Figures 9.40 and 9.41 show the timing in buffer operation.
TCNT
n
n+1
Compare match signal TGRA, TGRB TGRC, TGRD
n
N
N
Figure 9.40 Buffer Operation Timing (Compare Match)
Input capture signal
TCNT TGRA, TGRB TGRC, TGRD
N
N+1
n
N
N+1
n
N
Figure 9.41 Buffer Operation Timing (Input Capture)
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9. 16-Bit Timer Pulse Unit (TPU)
9.6.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 9.42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing.
TCNT input clock
TCNT
N
N+1
TGR
N
Compare match signal
TGF flag
TGI interrupt
Figure 9.42 TGI Interrupt Timing (Compare Match)
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9. 16-Bit Timer Pulse Unit (TPU)
TGF Flag Setting Timing in Case of Input Capture: Figure 9.43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 9.43 TGI Interrupt Timing (Input Capture)
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TCFV Flag/TCFU Flag Setting Timing: Figure 9.44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 9.45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 9.44 TCIV Interrupt Setting Timing
TCNT input clock TCNT (underflow) Underflow signal
H'0000
H'FFFF
TCFU flag
TCIU interrupt
Figure 9.45 TCIU Interrupt Setting Timing
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9. 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.46 shows the timing for status flag clearing by the CPU, and figure 9.47 shows the timing for status flag clearing by the DTC.
TSR write cycle T1 T2
Address
TSR address
Write signal
Status flag
Interrupt request signal
Figure 9.46 Timing for Status Flag Clearing by CPU
DTC read cycle T1 T2
DTC write cycle T1 T2
Address
Source address
Destination address
Status flag
Interrupt request signal
Figure 9.47 Timing for Status Flag Clearing by DTC Activation
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9. 16-Bit Timer Pulse Unit (TPU)
9.7
Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.48 shows the input clock conditions in phase counting mode.
Phase Phase differdifference Overlap ence
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more : 2.5 states or more Pulse width
Figure 9.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f : Counter frequency : Operating frequency N : TGR set value
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9. 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.49 shows the timing in this case.
TCNT write cycle T2 T1
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 9.49 Contention between TCNT Write and Clear Operations
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9. 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.50 shows the timing in this case.
TCNT write cycle T2 T1
Address
TCNT address
Write signal TCNT input clock N TCNT write data M
TCNT
Figure 9.50 Contention between TCNT Write and Increment Operations
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9. 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 9.51 shows the timing in this case.
TGR write cycle T2 T1 Address TGR address
Write signal Compare match signal TCNT N N+1
Prohibited
TGR
N TGR write data
M
Figure 9.51 Contention between TGR Write and Compare Match
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Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 9.52 shows the timing in this case.
TGR write cycle T2 T1 Address Buffer register address
Write signal Compare match signal Buffer register write data Buffer register TGR N M
N
Figure 9.52 Contention between Buffer Register Write and Compare Match
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9. 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9.53 shows the timing in this case.
TGR read cycle T2 T1 Address TGR address
Read signal Input capture signal TGR X M
Internal data bus
M
Figure 9.53 Contention between TGR Read and Input Capture
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Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.54 shows the timing in this case.
TGR write cycle T2 T1 Address TGR address
Write signal Input capture signal TCNT M
TGR
M
Figure 9.54 Contention between TGR Write and Input Capture
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Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.55 shows the timing in this case.
Buffer register write cycle T1 T2 Address Buffer register address
Write signal Input capture signal TCNT N
TGR Buffer register
M
N
M
Figure 9.55 Contention between Buffer Register Write and Input Capture
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9. 16-Bit Timer Pulse Unit (TPU)
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
TCNT input clock TCNT Counter clear signal TGF Prohibited TCFV H'FFFF H'0000
Figure 9.56 Contention between Overflow and Counter Clearing
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Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 9.57 shows the operation timing when there is contention between TCNT write and overflow.
TCNT write cycle T1 T2
Address
TCNT address
Write signal
TCNT write data H'FFFF Prohibited M
TCNT
TCFV flag
Figure 9.57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2355 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode.
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10. 8-Bit Timers
Section 10 8-Bit Timers
10.1 Overview
The H8S/2355 Group includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 10.1.1 Features
The features of the 8-bit timer module are listed below. * Selection of four clock sources The counters can be driven by one of three internal clock signals (/8, /64, or /8192) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal. * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output. * Provision for cascading of two channels Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode). Channel 1 can be used to count channel 0 compare matches (compare match count mode). * Three independent interrupts Compare match A and B and overflow interrupts can be requested independently. * A/D converter conversion start trigger can be generated Channel 0 compare match A signal can be used as an A/D converter conversion start trigger. * Module stop mode can be set As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting module stop mode.
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10. 8-Bit Timers
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of the 8-bit timer module.
External clock source TMCI0 TMCI1 Internal clock sources /8 /64 /8192
Clock select
Clock 1 Clock 0 TCORA0 Compare match A1 Compare match A0 Comparator A0 Overflow 1 Overflow 0 Clear 0 Compare match B1 Compare match B0 Comparator B0
Internal bus
TCORA1
Comparator A1
TMO0 TMRI0
TCNT0 Clear 1
TCNT1
Comparator B1
TMO1 TMRI1
Control logic
TCORB0 A/D conversion start request signal
TCORB1
TCSR0
TCSR1
TCR0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals
TCR1
Figure 10.1 Block Diagram of 8-Bit Timer
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10. 8-Bit Timers
10.1.3
Pin Configuration
Table 10.1 summarizes the input and output pins of the 8-bit timer. Table 10.1 Input and Output Pins of 8-Bit Timer
Channel 0 Name Timer output pin 0 Timer clock input pin 0 Timer reset input pin 0 1 Timer output pin 1 Timer clock input pin 1 Timer reset input pin 1 Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Outputs at compare match Inputs external clock for counter Inputs external reset to counter Outputs at compare match Inputs external clock for counter Inputs external reset to counter
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10. 8-Bit Timers
10.1.4
Register Configuration
Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers
Channel 0 Name Timer control register 0 Abbreviation TCR0 R/W R/W R/(W)* R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W
2 2
Initial value H'00 H'00 H'FF H'FF H'00 H'00 H'10 H'FF H'FF H'00 H'3FFF
Address* H'FFB0 H'FFB2 H'FFB4 H'FFB6 H'FFB8 H'FFB1 H'FFB3 H'FFB5 H'FFB7 H'FFB9 H'FF3C
1
Timer control/status register 0 TCSR0 Time constant register A0 Time constant register B0 Timer counter 0 1 Timer control register 1 TCORA0 TCORB0 TCNT0 TCR1
Timer control/status register 1 TCSR1 Time constant register A1 Time constant register B1 Timer counter 1 All Module stop control register TCORA1 TCORB1 TCNT1 MSTPCR
Notes: 1. Lower 16 bits of the address 2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 and channel 1 is a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word transfer instruction.
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10. 8-Bit Timers
10.2
10.2.1
Register Descriptions
Timer Counters 0 and 1 (TCNT0, TCNT1)
TCNT0 TCNT1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Bit
:
15 0
14 0
13 0
12 0
11 0
Initial value: R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 of TCR. The CPU can read or write to TCNT0 and TCNT1 at all times. TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word transfer instruction. TCNT0 and TCNT1 can be cleared by an external reset input or by a compare match signal. Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 of TCR. When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode. 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1)
TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORA1 4 1 3 1 2 1 1 1 0 1
Initial value: R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag of TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle.
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10. 8-Bit Timers
The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 of TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)
TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORB1 4 1 3 1 2 1 1 1 0 1
Initial value: R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag of TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle. The timer output can be freely controlled by these compare match signals and the settings of output select bits OS3 and OS2 of TCSR. TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode. 10.2.4
Bit
Time Control Registers 0 and 1 (TCR0, TCR1)
: 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value: R/W :
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at which TCNT is cleared, and enable interrupts. TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode. For details of this timing, see section 10.3, Operation.
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10. 8-Bit Timers
Bit 7--Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1.
Bit 7 CMIEB 0 1 Description CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled (Initial value)
Bit 6--Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1.
Bit 6 CMIEA 0 1 Description CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled (Initial value)
Bit 5--Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag of TCSR is set to 1.
Bit 5 OVIE 0 1 Description OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled (Initial value)
Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared: by compare match A or B, or by an external reset input.
Bit 4 CCLR1 0 Bit 3 CCLR0 0 1 1 0 1 Description Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input (Initial value)
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10. 8-Bit Timers
Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (): /8, /64, and /8192. The falling edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1.
Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Clock input disabled Internal clock, counted at falling edge of /8 Internal clock, counted at falling edge of /64 Internal clock, counted at falling edge of /8192 For channel 0: count at TCNT1 overflow signal* For channel 1: count at TCNT0 compare match A* External clock, counted at rising edge External clock, counted at falling edge External clock, counted at both rising and falling edges (Initial value)
If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.
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10. 8-Bit Timers
10.2.5
TCSR0
Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
Bit
:
7 CMFB 0 R/(W)*
6 CMFA 0 R/(W)*
5 OVF 0 R/(W)*
4 ADTE 0 R/W
3 OS3 0 R/W
2 OS2 0 R/W
1 OS1 0 R/W
0 OS0 0 R/W
Initial value: R/W :
TCSR1
Bit
:
7 CMFB 0 R/(W)*
6 CMFA 0 R/(W)*
5 OVF 0 R/(W)*
4 -- 1 --
3 OS3 0 R/W
2 OS2 0 R/W
1 OS1 0 R/W
0 OS0 0 R/W
Initial value : R/W :
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode. Bit 7--Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match.
Bit 7 CMFB 0 Description [Clearing conditions] * * 1 Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 (Initial value)
[Setting condition] Set when TCNT matches TCORB
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10. 8-Bit Timers
Bit 6--Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match.
Bit 6 CMFA 0 Description [Clearing conditions] * * 1 Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 (Initial value)
[Setting condition] Set when TCNT matches TCORA
Bit 5--Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00).
Bit 5 OVF 0 1 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 (Initial value)
Bit 4--A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare-match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified.
Bit 4 ADTE 0 1 Description A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled (Initial value)
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10. 8-Bit Timers
Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare match of TCOR and TCNT. Bits OS3 and OS2 select the effect of compare match B on the output level, bits OS1 and OS0 select the effect of compare match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: toggle output > 1 output > 0 output. If compare matches occur simultaneously, the output changes according to the compare match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare match event occurs.
Bit 3 OS3 0 Bit 2 OS2 0 1 1 0 1 Description No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) (Initial value)
Bit 1 OS1 0
Bit 0 OS0 0 1 Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value)
1
0 1
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10. 8-Bit Timers
10.2.6
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 12--Module Stop (MSTP12): Specifies the 8-bit timer stop mode.
Bit 12 MSTP12 0 1 Description 8-bit timer module stop mode cleared 8-bit timer module stop mode set (Initial value)
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10. 8-Bit Timers
10.3
10.3.1
Operation
TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (/8, /64, or /8192) divided from the system clock () can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10.2 shows the count timing.
Internal clock
Clock input to TCNT
TCNT
N-1
N
N+1
Figure 10.2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
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10. 8-Bit Timers
Figure 10.3 shows the timing of incrementation at both edges of an external clock signal.
External clock input
Clock input to TCNT
TCNT
N-1
N
N+1
Figure 10.3 Count Timing for External Clock Input 10.3.2 Compare Match Timing
Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 10.4 shows this timing.
TCNT
N
N+1
TCOR Compare match signal
N
CMF
Figure 10.4 Timing of CMF Setting
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10. 8-Bit Timers
Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 10.5 shows the timing when the output is set to toggle at compare match A.
Compare match A signal
Timer output pin
Figure 10.5 Timing of Timer Output Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.6 shows the timing of this operation.
Compare match signal
TCNT
N
H'00
Figure 10.6 Timing of Compare Match Clear
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10. 8-Bit Timers
10.3.3
Timing of External RESET on TCNT
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7 shows the timing of this operation.
External reset input pin
Clear signal
TCNT
N-1
N
H'00
Figure 10.7 Timing of External Reset 10.3.4 Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 10.8 shows the timing of this operation.
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 10.8 Timing of OVF Setting
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10. 8-Bit Timers
10.3.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare match flags The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs. The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set. The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare match conditions. Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A's for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Note on Usage: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes.
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10. 8-Bit Timers
10.4
10.4.1
Interrupts
Interrupt Sources and DTC Activation
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in Table 10.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 10.3 8-Bit Timer Interrupt Sources
Channel 0 Interrupt Source CMIA0 CMIB0 OVI0 1 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Priority High
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
10.4.2
A/D Converter Activation
The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.
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10. 8-Bit Timers
10.5
Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 10.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required.
TCNT H'FF TCORA TCORB H'00 Counter clear
TMO
Figure 10.9 Example of Pulse Output
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10. 8-Bit Timers
10.6
Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 10.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 10.10 shows this operation.
TCNT write cycle by CPU T1 T2
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 10.10 Contention between TCNT Write and Clear
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10. 8-Bit Timers
10.6.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 10.11 shows this operation.
TCNT write cycle by CPU T1 T2
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 10.11 Contention between TCNT Write and Increment
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10. 8-Bit Timers
10.6.3
Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 10.12 shows this operation.
TCOR write cycle by CPU T1 T2
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data Compare match signal Prohibited
Figure 10.12 Contention between TCOR Write and Compare Match
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10. 8-Bit Timers
10.6.4
Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 10.4. Table 10.4 Timer Output Priorities
Output Setting Toggle output 1 output 0 output No change Low Priority High
10.6.5
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 10.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 10.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks.
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10. 8-Bit Timers
Table 10.5 Switching of Internal Clock and TCNT Operation
Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from 1 low to low*
Clock before switchover Clock after switchover TCNT clock
No. 1
TCNT
N CKS bit write
N+1
2
Switching from 2 low to high*
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2 CKS bit write
3
Switching from 3 high to low*
Clock before switchover Clock after switchover
*4
TCNT clock
TCNT
N
N+1 CKS bit write
N+2
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10. 8-Bit Timers Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from high to high
Clock before switchover Clock after switchover TCNT clock
No. 4
TCNT
N
N+1
N+2 CKS bit write
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
10.6.6
Usage Note
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled before entering module stop mode.
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10. 8-Bit Timers
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11. Watchdog Timer
Section 11 Watchdog Timer
11.1 Overview
The H8S/2355 Group has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2355 Group. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 11.1.1 Features
WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode * WDTOVF output when in watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire H8S/2355 Group is reset at the same time. This internal reset can be a power-on reset or a manual reset. * Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt. * Choice of eight counter clock sources.
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11. Watchdog Timer
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the WDT.
Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select
WDTOVF Internal reset signal*
Reset control
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources
RSTCSR
TCNT
TSCR
Module bus
Bus interface
WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected.
Figure 11.1 Block Diagram of WDT
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Internal bus
11. Watchdog Timer
11.1.3
Pin Configuration
Table 11.1 describes the WDT output pin. Table 11.1 WDT Pin
Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs counter overflow signal in watchdog timer mode
11.1.4
Register Configuration
The WDT has three registers, as summarized in table 11.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 11.2 WDT Registers
Address* Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W R/(W)* R/W R/(W)*
3 3 1
Initial Value H'18 H'00 H'1F
Write*
2
Read H'FFBC H'FFBD H'FFBF
H'FFBC H'FFBC H'FFBE
Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 11.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag.
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11. Watchdog Timer
11.2
11.2.1
Bit
Register Descriptions
Timer Counter (TCNT)
: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Initial value : R/W :
TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. 11.2.2
Bit
Timer Control/Status Register (TCSR)
: 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value : R/W :
Note: * Can only be written with 0 for flag clearing.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access.
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11. Watchdog Timer
Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation.
Bit 7 OVF 0 1 Description [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode (Initial value)
Bit 6--Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal when TCNT overflows.
Bit 6 WT/IT 0 1 Note: * Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) Watchdog timer: Generates the WDTOVF signal when TCNT overflows* For details of the case where TCNT overflows in watchdog timer mode, see section 11.2.3, Reset Control/Status Register (RSTCSR).
Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value)
Bits 4 and 3--Reserved: Read-only bits, always read as 1.
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11. Watchdog Timer
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (), for input to TCNT.
Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Clock /2 (initial value) /64 /128 /512 /2048 /8192 /32768 /131072 Overflow Period (when = 20 MHz)* 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s
The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.
11.2.3
Bit
Reset Control/Status Register (RSTCSR)
: 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Initial value: R/W :
Note: * Can only be written with 0 for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access.
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11. Watchdog Timer
Bit 7--Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7 WOVF 0 1 Description [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation (Initial value)
Bit 6--Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2355 Group if TCNT overflows during watchdog timer operation.
Bit 6 RSTE 0 1 Note: * Description Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows The modules within the H8S/2355 Group are not reset, but TCNT and TCSR within the WDT are reset. (Initial value)
Bit 5--Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of resets, see section 4, Exception Handling.
Bit 5 RSTS 0 1 Description Power-on reset Manual reset (Initial value)
Bits 4 to 0--Reserved: Read-only bits, always read as 1.
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11. Watchdog Timer
11.2.4
Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 11.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR.
TCNT write 15 Address: H'FFBC H'5A 87 Write data 0
TCSR write 15 Address: H'FFBC H'A5 87 Write data 0
Figure 11.2 Format of Data Written to TCNT and TCSR
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11. Watchdog Timer
Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 11.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF bit.
Writing 0 to WOVF bit 15 Address: H'FFBE H'A5 87 H'00 0
Writing to RSTE and RSTS bits 15 Address: H'FFBE H'5A 87 Write data 0
Figure 11.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.
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11. Watchdog Timer
11.3
11.3.1
Operation
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This is shown in figure 11.4. This WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2355 Group internally is generated at the same time as the WDTOVF signal. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
TCNT count
Overflow
H'FF
H'00 WT/IT=1 TME=1 H'00 written to TCNT
Time
WOVF=1 WDTOVF and internal reset are generated
WT/IT=1 TME=1
H'00 written to TCNT
WDTOVF signal
132 states*2
Internal reset signal*1 Legend: WT/IT : Timer mode select bit TME : Timer enable bit 518 states
Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0.
Figure 11.4 Watchdog Timer Operation
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11. Watchdog Timer
11.3.2
Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 11.5. This function can be used to generate interrupt requests at regular intervals.
TCNT count H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI
Time
Legend: WOVI: Interval timer interrupt request generation
Figure 11.5 Interval Timer Operation
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11. Watchdog Timer
11.3.3
Timing of Setting Overflow Flag (OVF)
The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 11.6.
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 11.6 Timing of Setting of OVF
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11. Watchdog Timer
11.3.4
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2355 Group chip. Figure 11.7 shows the timing in this case.
TCNT
H'FF
H'00
Overflow signal (internal signal)
WOVF
WDTOVF signal
132 states
Internal reset signal
518 states
Figure 11.7 Timing of Setting of WOVF
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11. Watchdog Timer
11.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
11.5
11.5.1
Usage Notes
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation.
TCNT write cycle T1 T2
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.8 Contention between TCNT Write and Increment 11.5.2 Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.
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11. Watchdog Timer
11.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 11.5.4 System Reset by WDTOVF Signal
If the WDTOVF output signal is input to the RES pin of the H8S/2355 Group, the H8S/2355 Group will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 11.9.
H8S/2355 RES
Reset input
Reset signal to entire system
WDTOVF
Figure 11.9 Circuit for System Reset by WDTOVF Signal (Example) 11.5.5 Internal Reset in Watchdog Timer Mode
The H8S/2355 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
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11. Watchdog Timer
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12. Serial Communication Interface (SCI)
Section 12 Serial Communication Interface (SCI)
12.1 Overview
The H8S/2355 Group is equipped with a 3-channel serial communication interface (SCI). All three channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 12.1.1 Features
SCI features are listed below. * Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode Serial data communication executed using asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length Stop bit length Parity Multiprocessor bit Break detection Clocked Synchronous mode Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length : 8 bits Overrun errors detected
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: : : : :
7 or 8 bits 1 or 2 bits Even, odd, or none 1 or 0 Parity, overrun, and framing errors Break can be detected by reading the RxD pin level directly in case of a framing error
Receive error detection :
Receive error detection :
12. Serial Communication Interface (SCI)
* Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * Choice of LSB-first or MSB-first transfer Can be selected regardless of the communication mode* (except in the case of asynchronous mode bit data) * On-chip baud rate generator allows any bit rate to be selected * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources Four interrupt sources -- transmit-data-empty, transmit-end, receive-data-full, and receive error -- that can issue requests independently The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) to execute data transfer * Module stop mode can be set As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. Note: * Descriptions in this section refer to LSB-first transfer.
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12. Serial Communication Interface (SCI)
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the SCI.
Bus interface
Module data bus
Internal data bus
RDR
TDR
RxD
RSR
TSR
SCMR SSR SCR SMR
Transmission/ reception control
BRR Baud rate generator /4 /16 /64 Clock
TxD
Parity generation Parity check
SCK
External clock TEI TXI RXI ERI
Legend: SCMR : Smart Card mode register : Receive shift register RSR : Receive data register RDR : Transmit shift register TSR : Transmit data register TDR : Serial mode register SMR : Serial control register SCR : Serial status register SSR : Bit rate register BRR
Figure 12.1 Block Diagram of SCI
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12. Serial Communication Interface (SCI)
12.1.3
Pin Configuration
Table 12.1 shows the serial pins for each SCI channel. Table 12.1 SCI Pins
Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output
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12. Serial Communication Interface (SCI)
12.1.4
Register Configuration
The SCI has the internal registers shown in table 12.2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 12.2 SCI Registers
Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W
2 2 2
Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF
Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C
1
Smart card mode register 0 SCMR0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1
Smart card mode register 1 SCMR1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2
Smart card mode register 2 SCMR2 All Module stop control register MSTPCR Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.
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12. Serial Communication Interface (SCI)
12.2
12.2.1
Bit R/W
Register Descriptions
Receive Shift Register (RSR)
: : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 12.2.2
Bit
Receive Data Register (RDR)
: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Initial value : R/W :
RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode.
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12. Serial Communication Interface (SCI)
12.2.3
Bit R/W
Transmit Shift Register (TSR)
: : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 12.2.4
Bit
Transmit Data Register (TDR)
: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
Initial value : R/W :
TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode.
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12. Serial Communication Interface (SCI)
12.2.5
Bit
Serial Mode Register (SMR)
: 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value : R/W :
SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7--Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode.
Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value)
Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. (Initial value)
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12. Serial Communication Interface (SCI)
Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
Bit 5 PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. (Initial value)
Bit 4--Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode.
Bit 4 O/E 0 1 Description Even parity* Odd parity*
2 1
(Initial value)
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.
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12. Serial Communication Interface (SCI)
Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added.
Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value)
2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication Function.
Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value)
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12. Serial Communication Interface (SCI)
Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from , /4, /16, and /64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 12.2.8, Bit Rate Register (BRR).
Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description clock /4 clock /16 clock /64 clock (Initial value)
12.2.6
Bit
Serial Control Register (SCR)
: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
Initial value : R/W :
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode or module stop mode.
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12. Serial Communication Interface (SCI)
Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1.
Bit 7 TIE 0 1 Note: * Description Transmit data empty interrupt (TXI) requests disabled* Transmit data empty interrupt (TXI) requests enabled TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. (Initial value)
Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6 RIE 0 1 Note: * Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5 TE 0 1 Description Transmission disabled* Transmission enabled*
1
(Initial value)
2
Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1.
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12. Serial Communication Interface (SCI)
Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4 RE 0 1 Description Reception disabled* Reception enabled*
1
(Initial value)
2
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1.
Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When MPB = 1 data is received (Initial value)
Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received.
Note:
*
When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
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12. Serial Communication Interface (SCI)
Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission.
Bit 2 TEIE 0 1 Note: * Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. (Initial value)
Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 12.9.
Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port*
1
Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output* Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input
3 3 2
Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Rev.4.00 Feb. 13, 2007 Page 434 of 846 REJ09B0354-0400
12. Serial Communication Interface (SCI)
12.2.7
Bit
Serial Status Register (SSR)
: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Initial value : R/W :
Note: Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR.
Bit 7 TDRE 0 Description [Clearing conditions] * * 1 * * When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR
[Setting conditions]
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12. Serial Communication Interface (SCI)
Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6 RDRF 0 Description [Clearing conditions] * * 1 When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and reads data from RDR (Initial value)
[Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination.
Bit 5 ORER 0 1 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*
1
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12. Serial Communication Interface (SCI)
Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination.
Bit 4 FER 0 1 Description [Clearing condition] * When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when 2 reception ends, and the stop bit is 0 * Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*
1
Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination.
Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 (Initial value)*
1
[Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not 2 match the parity setting (even or odd) specified by the O/E bit in SMR*
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
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12. Serial Communication Interface (SCI)
Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified.
Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
[Setting conditions]
Bit 1--Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified.
Bit 1 MPB 0 1 Note: * Description [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. (Initial value)*
Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode.
Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value)
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12. Serial Communication Interface (SCI)
12.2.8
Bit
Bit Rate Register (BRR)
: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
Initial value : R/W :
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel.
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12. Serial Communication Interface (SCI)
Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR settings in clocked synchronous mode. Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
= 2 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- = 2.097152 MHz Error (%) = 2.4576 MHz Error (%) = 3 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 --
n 1 1 0 0 0 0 0 0 0 0 0
N 141 103 207 103 51 25 12 6 2 1 1
n 1 1 0 0 0 0 0 0 0 0 0
N 148 108 217 108 54 26 13 6 2 1 1
n
N 174 127 255 127 63 31 15 7 3 1 1
n
N 212 155 77 155 77 38 19 9 4 2 --
-0.04 1 0.21 0.21 0.21 1 0 0
-0.26 1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 1 1 0 0 0 0 0 0 0 --
-0.70 0 1.14 0
-2.48 0 -2.48 0 -- -- -- 0 0 0
= 3.6864 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00
= 4 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 --
= 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
= 5 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
n 2 1 1 0 0 0 0 0 0 -- 0
N 64 191 95 191 95 47 23 11 5 -- 2
n 2 1 1 0 0 0 0 0 0 0 0
N 70 207 103 207 103 51 25 12 6 3 2
n 2 1 1 0 0 0 0 0 0 0 0
N 86 255 127 255 127 63 31 15 7 4 3
n 2 2 1 1 0 0 0 0 0
N 88 64 129 64 129 64 32 15 7 4 3
-1.70 0 0.00 0
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12. Serial Communication Interface (SCI)
= 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 = 7.3728 MHz Error (%) = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 --
n 2 2 1 1 0 0 0 0 0 0 0
N 106 77 155 77 155 77 38 19 9 5 4
n
N 108 79 159 79 159 79 39 19 9 5 4
n 2 2 1 1 0 0 0 0 0 0 0
N 130 95 191 95 191 95 47 23 11 6 5
n
N 141 103 207 103 207 103 51 25 12 7 6
-0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0
-0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 1 1 0 0 0 0 0 0 0
-2.34 0 -2.34 0 0.00 0
-2.34 0
= 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%)
= 10 MHz Error (%)
= 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16
= 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
n 2 2 1 1 0 0 0 0 0 0 0
N 174 127 255 127 255 127 63 31 15 9 7
n
N 177 129 64 129 64 129 64 32 15 9 7
n
N 212 155 77 155 77 155 77 38 19 11 9
n 2 2 2 1 1 0 0 0
N 217 159 79 159 79 159 79 39 19 11 9
-0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0
-0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0
-1.36 0 1.73 0.00 1.73 0 0 0
-2.34 0 0.00 0
-1.70 0 0.00 0
-2.34 0
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12. Serial Communication Interface (SCI)
= 14 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 = 16 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00
n 2 2 2 1 1 0 0 0 0 0 0
N 248 181 90 181 90 181 90 45 22 13 10
n
N 64 191 95 191 95 191 95 47 23 14 11
n 3 2 2 1 1 0 0 0 0
N 70 207 103 207 103 207 103 51 25 15 12
n 3 2 2 1 1 0 0 0 0 0 0
N 75 223 111 223 111 223 111 55 27 16 13
-0.17 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0
-0.93 0 -0.93 0 0.00 -- 0 0
-1.70 0 0.00 0
= 18 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%)
= 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
= 20 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
n 3 2 2 1 1 0 0 0 0 0 0
N 79 233 116 233 116 233 116 58 28 17 14
n
N 86 255 127 255 127 255 127 63 31 19 15
n 3 3 2 2 1 1 0 0 0
N 88 64 129 64 129 64 129 64 32 19 15
-0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0
-0.69 0 1.02 0.00 0 0
-1.70 0 0.00 0
-2.34 0
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12. Serial Communication Interface (SCI)
Table 12.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n 3 2 1 1 0 0 0 0 0 0 0 0 = 2 MHz N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 = 4 MHz N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 -- 124 249 124 199 99 199 79 39 19 7 3 1 -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 -- -- -- 249 124 249 99 49 24 9 4 -- 0* 3 3 2 2 1 1 0 0 0 0 0 0 -- -- 249 124 249 99 199 99 159 79 39 15 7 3 -- -- -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n = 8 MHz N n = 10 MHz N n = 16 MHz N n = 20 MHz N
Legend: Blank : Cannot be set. -- : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. Note: As far as possible, the setting should be made so that the error is no more than 1%.
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12. Serial Communication Interface (SCI)
The BRR setting is found from the following formulas. Asynchronous mode: N= 64 x 2
2n - 1
xB
x 10 - 1
6
Clocked synchronous mode: N= Where B: N: : n: 8x2
2n - 1
xB
x 10 - 1
6
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.)
SMR Setting
n 0 1 2 3
Clock /4 /16 /64
CKS1 0 0 1 1
CKS0 0 1 0 1
The bit rate error in asynchronous mode is found from the following formula: Error (%) = { x 10
6 2n - 1
(N + 1) x B x 64 x 2
- 1} x 100
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12. Serial Communication Interface (SCI)
Table 12.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12. Serial Communication Interface (SCI)
Table 12.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
(MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500
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12. Serial Communication Interface (SCI)
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
(MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3
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12. Serial Communication Interface (SCI)
12.2.9
Bit
Smart Card Mode Register (SCMR)
: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W
Initial value : R/W :
SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see 13.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format.
Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value)
Bit 2--Smart Card Data Invert (SINV): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit.
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12. Serial Communication Interface (SCI)
12.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Module Stop (MSTP7): Specifies the SCI channel 2 module stop mode.
Bit 7 MSTP7 0 1 Description SCI channel 2 module stop mode cleared SCI channel 2 module stop mode set (Initial value)
Bit 6--Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode.
Bit 6 MSTP6 0 1 Description SCI channel 1 module stop mode cleared SCI channel 1 module stop mode set (Initial value)
Bit 5--Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode.
Bit 5 MSTP5 0 1 Description SCI channel 0 module stop mode cleared SCI channel 0 module stop mode set (Initial value) Rev.4.00 Feb. 13, 2007 Page 449 of 846 REJ09B0354-0400
12. Serial Communication Interface (SCI)
12.3
12.3.1
Operation
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 12.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 12.9. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock
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12. Serial Communication Interface (SCI)
Table 12.8 SMR Settings and Serial Transfer Format Selection
SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- -- 1 -- -- 1 -- -- -- 0 1 0 1 -- Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Yes SCI Transfer Format Multi Processor Bit No
Data Length 8-bit data
Parity Bit No
Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits
7-bit data
1 bit 2 bits None
Table 12.9 SMR and SCR Settings and SCI Clock Source Selection
SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synchronous mode Internal Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock
SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate
External
Inputs clock with frequency of 16 times the bit rate Outputs serial clock
External
Inputs serial clock
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12. Serial Communication Interface (SCI)
12.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit.
Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1
Stop bit
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
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12. Serial Communication Interface (SCI)
Data Transfer Format: Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 12.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1
S
Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
STOP
S
STOP STOP
S
P STOP
S
P STOP STOP
S
S
STOP STOP
S
P
STOP
S
P
STOP STOP
S
MPB STOP
S
MPB STOP STOP
S
MPB STOP
S
MPB STOP STOP
Legend: S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit Rev.4.00 Feb. 13, 2007 Page 453 of 846 REJ09B0354-0400
12. Serial Communication Interface (SCI)
Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.3.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 12.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations: * SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain.
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12. Serial Communication Interface (SCI)
Figure 12.4 shows a sample SCI initialization flowchart.
Start initialization
Clear TE and RE bits in SCR to 0
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[4]
Set CKE1 and CKE0 bits in SCR (TE, RE bits 0)
[1]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2] [3]
No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits

Figure 12.4 Sample SCI Initialization Flowchart
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12. Serial Communication Interface (SCI)
* Serial data transmission (asynchronous mode) Figure 12.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
No
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and date is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes Read TEND flag in SSR
[3]
No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1
[4]
Clear TE bit in SCR to 0
Figure 12.5 Sample Serial Transmission Flowchart
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12. Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
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12. Serial Communication Interface (SCI)
Figure 12.6 shows an example of the operation for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1
1 Idle state (mark state)
TDRE
TEND
TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated
TEI interrupt request generated
1 frame
Figure 12.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
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12. Serial Communication Interface (SCI)
* Serial data reception (asynchronous mode) Figure 12.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception.
Initialization Start reception [1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER FER ORER = 1 ORER, PER, and FER flags are all [3] cleared to 0. Reception cannot be No Error processing resumed if any of these flags are (Continued on next page) set to 1. In the case of a framing error, a break can be detected by reading the value of the input port [4] Read RDRF flag in SSR corresponding to the RxD pin.
No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
SCI status check and receive data [4] read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation [5] procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by an RXI interrupt and the RDR value is read.
No All data received? Yes Clear RE bit in SCR to 0 [5]
Figure 12.7 Sample Serial Reception Data Flowchart
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12. Serial Communication Interface (SCI)
[3] Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
No PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 12.7 Sample Serial Reception Data Flowchart (cont)
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12. Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 12.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated.
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12. Serial Communication Interface (SCI)
Table 12.11 Receive Errors and Conditions for Occurrence
Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer
When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to RDR. in SSR is set to 1 When the stop bit is 0 Receive data is transferred from RSR to RDR.
Framing error Parity error
FER PER
When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR
Figure 12.8 shows an example of the operation for reception in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1
Idle state (mark state)
RDRF
FER
RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ERI interrupt request generated by framing error
1 frame
Figure 12.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
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12. Serial Communication Interface (SCI)
12.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors.
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12. Serial Communication Interface (SCI)
Figure 12.9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 12.10. Clock: See the section on asynchronous mode.
Transmitting station Serial transmission line
Receiving station A (ID = 01) Serial data
Receiving station B (ID = 02)
Receiving station C (ID = 03)
Receiving station D (ID = 04)
H'01 (MPB = 1) ID transmission cycle = receiving station specification
H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID
Legend: MPB: Multiprocessor bit
Figure 12.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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12. Serial Communication Interface (SCI)
Data Transfer Operations: * Multiprocessor serial data transmission Figure 12.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission.
Initialization Start transmission [1] [1] SCI initialization:
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR
[2]
The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0.
Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1
[3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE [3] flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0.
[4]
Clear TE bit in SCR to 0
Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart
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12. Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated.
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12. Serial Communication Interface (SCI)
Figure 12.11 shows an example of SCI operation for transmission using the multiprocessor format.
Multiprocessor Stop bit bit D7 0/1 1
1
Start bit 0 D0 D1
Data
Start bit 0 D0 D1
Data D7
Multiproces- Stop 1 sor bit bit 0/1 1
Idle state (mark state)
TDRE
TEND
TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated
TEI interrupt request generated
1 frame
Figure 12.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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12. Serial Communication Interface (SCI)
* Multiprocessor serial data reception Figure 12.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception.
Initialization Start reception [1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value.
Read MPIE bit in SCR Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR
[2]
Yes
[3]
FER ORER = 1 No Read RDRF flag in SSR
Yes
[4] No
RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0
[5] Error processing (Continued on next page)
Figure 12.12 Sample Multiprocessor Serial Reception Flowchart
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12. Serial Communication Interface (SCI)
[5]
Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
Clear ORER, PER, and FER flags in SSR to 0

Figure 12.12 Sample Multiprocessor Serial Reception Flowchart (cont)
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12. Serial Communication Interface (SCI)
Figure 12.13 shows an example of SCI operation for multiprocessor format reception.
Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit
1
1
1 Idle state (mark state)
MPIE
RDRF
RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated
RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state
(a) Data does not match station's ID
1
Start bit
Data (ID2)
MPB D0 D1 D7 1
Stop bit 1
Start bit 0 D0
Data (Data2) MPB D1 D7 0
Stop bit
1
0
1 Idle state (mark state)
MPIE
RDRF
RDR value
ID1
ID2
Data2 MPIE bit set to 1 again
MPIE = 0
RXI interrupt request (multiprocessor interrupt) generated
RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine
(b) Data matches station's ID
Figure 12.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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12. Serial Communication Interface (SCI)
12.3.4
Operation in Clocked Synchronous Mode
In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.14 shows the general format for clocked synchronous serial communication.
One unit of transfer data (character or frame)
* *
Serial clock
LSB MSB
Serial data Don't care
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High except in continuous transfer
Figure 12.14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
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12. Serial Communication Interface (SCI)
Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Data Transfer Operations: * SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 12.15 shows a sample SCI initialization flowchart.
Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) Set data transfer format in SMR and SCMR Set value in BRR Wait 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] No
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[1]
[2]
[3]
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 12.15 Sample SCI Initialization Flowchart
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12. Serial Communication Interface (SCI)
* Serial data transmission (clocked synchronous mode) Figure 12.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Initialization Start transmission
[1]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR.
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes
Clear TE bit in SCR to 0

Figure 12.16 Sample Serial Transmission Flowchart
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12. Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 12.17 shows an example of SCI operation in transmission.
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE TEND TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame
TXI interrupt request generated
TEI interrupt request generated
Figure 12.17 Example of SCI Operation in Transmission
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12. Serial Communication Interface (SCI)
* Serial data reception (clocked synchronous mode) Figure 12.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
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12. Serial Communication Interface (SCI)
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Initialization Start reception
[1]
Read ORER flag in SSR Yes ORER = 1 No
[2]
[3] Error processing (Continued below)
[2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read.
Read RDRF flag in SSR
[4]
No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
No All data received? Yes Clear RE bit in SCR to 0 [5]
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
Figure 12.18 Sample Serial Reception Flowchart
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12. Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 12.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 12.19 shows an example of SCI operation in reception.
Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 12.19 Example of SCI Operation in Reception * Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations.
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[1] SCI initialization:
The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations.
Initialization Start transmission/reception
[1]
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
[2]
[2] SCI status check and transmit data
write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt.
[3] Receive error processing:
Read ORER flag in SSR Yes [3] Error processing
ORER = 1 No
If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data
[4] read:
Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception
Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4]
[5] continuation procedure:
To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read.
No All data received? Yes Clear TE and RE bits in SCR to 0 [5]
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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12. Serial Communication Interface (SCI)
12.4
SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 12.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
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12. Serial Communication Interface (SCI)
Table 12.12 SCI Interrupt Sources
Channel 0 Interrupt Source ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Note: * Description Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority* High
This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of the interrupt controller.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case.
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12. Serial Communication Interface (SCI)
12.5
Usage Notes
The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 12.13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 12.13 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer RSR to RDR X
Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR.
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12. Serial Communication Interface (SCI)
Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 12.21.
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12. Serial Communication Interface (SCI)
16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0
Receive data (RxD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | N (1 + F) | x 100 % ... Formula (1) Where M N D L F : Reception margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875 % is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 - 1 2 x 16 ) x 100 % ... Formula (2)
= 46.875 %
However, this is only the computed value, and a margin of 20 % to 30 % should be allowed in system design.
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12. Serial Communication Interface (SCI)
Restrictions on Use of DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clocks after TDR is updated. (Figure 12.22) * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI).
SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7
Note: When operating on an external clock, set t > 4 clocks.
Figure 12.22 Example of Clocked Synchronous Transmission by DTC
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13. Smart Card Interface
Section 13 Smart Card Interface
13.1 Overview
SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 13.1.1 Features
Features of the Smart Card interface supported by the H8S/2355 are as follows. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC) to execute data transfer
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13. Smart Card Interface
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the Smart Card interface.
Bus interface
Module data bus
Internal data bus
RDR
TDR
RxD
RSR
TSR
SCMR SSR SCR SMR
Transmission/ reception control
BRR Baud rate generator /4 /16 /64 Clock
TxD
Parity generation Parity check
SCK TXI RXI ERI
Legend: SCMR : Smart Card mode register : Receive shift register RSR : Receive data register RDR : Transmit shift register TSR : Transmit data register TDR : Serial mode register SMR : Serial control register SCR : Serial status register SSR : Bit rate register BRR
Figure 13.1 Block Diagram of Smart Card Interface
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13. Smart Card Interface
13.1.3
Pin Configuration
Table 13.1 shows the Smart Card interface pin configuration. Table 13.1 Smart Card Interface Pins
Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output
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13. Smart Card Interface
13.1.4
Register Configuration
Table 13.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 12, Serial Communication Interface (SCI). Table 13.2 Smart Card Interface Registers
Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W
2 2 2
Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF
Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C
1
Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.
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13. Smart Card Interface
13.2
Register Descriptions
Registers added with the Smart Card interface and bits for which the function changes are described here. 13.2.1
Bit
Smart Card Mode Register (SCMR)
: 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W
Initial value : R/W :
SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value)
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13. Smart Card Interface
Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 13.3.4, Register Settings.
Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value)
Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function.
Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value)
13.2.2
Bit
Serial Status Register (SSR)
: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Initial value : R/W :
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5--Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR).
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13. Smart Card Interface
Bit 4--Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode.
Bit 4 ERS 0 Description [Clearing conditions] * * 1 By a reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value)
[Setting condition] When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.
Bits 3 to 0--Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below.
Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * * * When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and write data to TDR By a reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 (Initial value)
[Setting conditions]
Note: etu: Elementary time unit (time for transfer of 1 bit)
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13. Smart Card Interface
13.2.3
Bit
Serial Mode Register (SMR)
: 7 GM 0 GM R/W 6 CHR 0 0 R/W 5 PE 0 1 R/W 4 O/E 0 O/E R/W 3 STOP 0 1 R/W 2 MP 0 0 R/W 1 CKS1 0 CKS1 R/W 0 CKS0 0 CKS0 R/W
Initial value : Set value* : R/W :
Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2.
The function of bit 7 of SMR changes in smart card interface mode. Bit 7--GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR).
Bit 7 GM 0 Description Normal smart card interface mode operation * * 1 * * TEND flag generation 12.5 etu after beginning of start bit Clock output ON/OFF control only TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) (Initial value)
GSM mode smart card interface mode operation
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bits 6 to 0--Operate in the same way as for the normal SCI. For details, see section 12.2.5, Serial Mode Register (SMR).
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13. Smart Card Interface
13.2.4
Bit
Serial Control Register (SCR)
: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
Initial value : R/W :
In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2--Operate in the same way as for the normal SCI. For details, see section 12.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low.
SCMR SMIF 0 1 1 1 1 1 1 SMR C/A, GM See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCR Setting CKE1 CKE0 SCK Pin Function
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13. Smart Card Interface
13.3
13.3.1
Operation
Overview
The main functions of the Smart Card interface are as follows. * One frame consists of 8-bit data plus a parity bit. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no clocked synchronous communication function.
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13. Smart Card Interface
13.3.2
Pin Connections
Figure 13.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground.
VCC TxD I/O RxD SCK Rx (port) H8S/2355 Connected equipment Data line Clock line Reset line CLK RST IC card
Figure 13.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.
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13. Smart Card Interface
13.3.3
Data Format
Figure 13.3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Transmitting station output Legend: Ds D0 to D7 Dp DE Receiving station output : Start bit : Data bits : Parity bit : Error signal
Figure 13.3 Smart Card Interface Data Format
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13. Smart Card Interface
The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data.
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13. Smart Card Interface
13.3.4
Register Settings
Table 13.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 13.3 Smart Card Interface Register Settings
Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF
Legend: --: Unused bit. Note: * The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 13.3.5, Clock. BRR Setting: BRR is used to set the bit rate. See section 13.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 12, Serial Communication Interface. Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
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13. Smart Card Interface
Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). * Direct convention (SDIR = SINV = O/E = 0)
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. * Inverse convention (SDIR = SINV = O/E = 1)
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2355, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception).
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13. Smart Card Interface
13.3.5
Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 13.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= 1488 x 2
2n - 1
x (N + 1)
x 10
6
Where: N = Value set in BRR (0 N 255) B = Bit rate (bit/s) = Operating frequency (MHz) n = See table 13.4 Table 13.4 Correspondence between n and CKS1, CKS0
n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1
Table 13.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0)
(MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961
Note: Bit rates are rounded to the nearest whole number.
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13. Smart Card Interface
The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 N 255, and the smaller error is specified. N= 1488 x 2
2n - 1
xB
x 10 - 1
6
Table 13.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0)
(MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 N Error 6.60
N Error N Error N Error 1 30 1 25 1 8.99
N Error N Error N Error 1 0.00 1 12.01 2
15.99 2
Table 13.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0
The bit rate error is given by the following formula: Error (%) = ( 1488 x 2
2n - 1
x B x (N + 1)
x 10 - 1) x 100
6
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13. Smart Card Interface
13.3.6
Data Transfer Operations
Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis.
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13. Smart Card Interface
Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 13.4 shows a flowchart for transmitting, and figure 13.5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 13.6. If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DTC below.
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13. Smart Card Interface
Start Initialization Start transmission
ERS = 0? Yes
No
Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No
All data transmitted? Yes No ERS = 0? Yes Error processing
No TEND = 1? Yes Clear TE bit to 0
End
Figure 13.4 Example of Transmission Processing Flow
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13. Smart Card Interface
TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 Data 1 ; Data remains in TDR Data 1 I/O signal line output TSR (shift register)
In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed.
Figure 13.5 Relation Between Transmit Operation and Internal Registers
I/O data TXI (TEND interrupt) When GM = 0
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE Guard time
12.5 etu
When GM = 1
11.0 etu
Legend: Ds D0 to D7 Dp DE
: Start bit : Data bits : Parity bit : Error signal
Figure 13.6 TEND Flag Generation Timing in Transmission Operation
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13. Smart Card Interface
Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 13.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0.
Start Initialization Start reception
ORER = 0 and PER = 0 Yes
No
Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0
No
All data received? Yes Clear RE bit to 0
Figure 13.7 Example of Reception Processing Flow
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13. Smart Card Interface
With the above processing, interrupt servicing or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GSM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
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13. Smart Card Interface
Figure 13.8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.
Specified pulse width Specified pulse width
SCK
SCR write (CKE0 = 0)
SCR write (CKE0 = 1)
Figure 13.8 Timing for Fixing Clock Output Level Interrupt Operation: There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 13.8. Table 13.8 Smart Card Mode Operating States and Interrupt Sources
Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DTC Activation Possible Not possible Possible Not possible
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13. Smart Card Interface
Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same data automatically. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 7, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 13.3.7 Operation in GSM Mode
Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. * When changing from smart card interface mode to software standby mode
[1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state.
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13. Smart Card Interface
*
When returning to smart card interface mode from software standby mode
[7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty.
Software standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5] [6]
[7] [8] [9]
Figure 13.9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output.
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13. Smart Card Interface
13.4
Usage Notes
The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card Interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 13.10.
372 clocks 186 clocks 0 185 371 0 185 371 0
Internal basic clock
Receive data (RxD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 13.10 Receive Data Sampling Timing in Smart Card Mode
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13. Smart Card Interface
Thus the reception margin in asynchronous mode is given by the following formula. M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100 %
Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 - 1/2 x 372) x 100 % = 49.866 % Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. * Retransfer operation when SCI is in receive mode Figure 13.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.
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13. Smart Card Interface
Transfer frame n + 1
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransferred frame
(DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4
[4]
[3]
Figure 13.11 Retransfer Operation in SCI Receive Mode * Retransfer operation when SCI is in transmit mode Figure 13.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared to 0.
Transfer frame n + 1 (DE) Ds D0 D1 D2 D3 D4
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6]
Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
Transfer to TSR from TDR [9]
[8]
Figure 13.12 Retransfer Operation in SCI Transmit Mode
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14. A/D Converter
Section 14 A/D Converter
14.1 Overview
The H8S/2355 Group incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 14.1.1 Features
A/D converter features are listed below * 10-bit resolution * Eight input channels * Settable analog conversion voltage range Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage * High-speed conversion Minimum conversion time: 6.7 s per channel (at 20-MHz operation) * Choice of single mode or scan mode Single mode: Scan mode: * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin * A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion * Module stop mode can be set As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Single-channel A/D conversion Continuous A/D conversion on 1 to 4 channels
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14. A/D Converter
14.1.2
Block Diagram
Figure 14.1 shows a block diagram of the A/D converter.
Module data bus
Bus interface
Internal data bus
AVCC Vref AVSS 10-bit D/A
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN0 AN1
Multiplexer
+ - Comparator Sample-andhold circuit ADI interrupt Control circuit
AN2 AN3 AN4 AN5 AN6 AN7
ADTRG
Conversion start trigger from 8-bit timer or TPU
Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D
Figure 14.1 Block Diagram of A/D Converter
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14. A/D Converter
14.1.3
Pin Configuration
Table 14.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 14.1 A/D Converter Pins
Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Group 0 analog inputs
A/D external trigger input pin ADTRG
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14. A/D Converter
14.1.4
Register Configuration
Table 14.2 summarizes the registers of the A/D converter. Table 14.2 A/D Converter Registers
Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR R/W R R R R R R R R R/(W)* R/W R/W
2
Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF
Address* H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C
1
Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing.
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14. A/D Converter
14.2
14.2.1
Bit
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : R/W :
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 14.3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 14.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 14.3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD
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14. A/D Converter
14.2.2
Bit
A/D Control/Status Register (ADCSR)
: 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Initial value : R/W :
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7 ADF 0 Description [Clearing conditions] * * 1 * * When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels (Initial value)
[Setting conditions]
Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion.
Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value)
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14. A/D Converter
Bit 5--A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG).
Bit 5 ADST 0 1 Description * * * A/D conversion stopped (Initial value)
Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode.
Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 14.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0).
Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value)
Bit 3--Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0).
Bit 3 CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value)
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14. A/D Converter
Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0).
Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7
14.2.3
Bit
A/D Control Register (ADCR)
: 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Initial value : R/W :
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode.
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14. A/D Converter
Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0).
Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled (Initial value)
Bits 5 to 0--Reserved: These bits are reserved; they are always read as 1 and cannot be modified. 14.2.4 Module Stop Control Register (MSTPCR)
MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9--Module Stop (MSTP9): Specifies the A/D converter module stop mode.
Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value)
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14. A/D Converter
14.3
Interface to Bus Master
ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 14.2 shows the data flow for ADDR access.
Upper byte read
Bus master (H'AA)
Bus interface
Module data bus
TEMP (H'40)
Note: n = A to D Lower byte read
ADDRnH (H'AA)
ADDRnL (H'40)
Bus master (H'40)
Module data bus Bus interface
TEMP (H'40)
Note: n = A to D
ADDRnH (H'AA)
ADDRnL (H'40)
Figure 14.2 ADDR Access Operation (Reading H'AA40)
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14. A/D Converter
14.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0)
Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 14.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated.
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14. A/D Converter
Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle
A/D conversion 1
A/D conversion starts
Set* Clear*
Set* Clear*
Idle
A/D conversion 2
Idle
ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2
Note: * Vertical arrows ( ) indicate instructions executed by software.
Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
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14. A/D Converter
14.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 14.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
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14. A/D Converter
Continuous A/D conversion execution
Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle
A/D conversion 1
Clear*1 Clear*1
Idle
A/D conversion 2
A/D conversion 4
Idle
A/D conversion 5 *2
Idle
A/D conversion 3
Idle Idle
Idle
Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
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14. A/D Converter
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D conversion timing. Table 14.4 indicates the A/D conversion time. As indicated in figure 14.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14.4. In scan mode, the values given in table 14.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
(1) Address bus (2)
Write signal
Input sampling timing
ADF tD t SPL t CONV Legend: (1) : (2) : : tD tSPL : tCONV :
ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time
Figure 14.5 A/D Conversion Timing
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14. A/D Converter
Table 14.4 A/D Conversion Time (Single Mode)
CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 10 -- 259 Typ -- 63 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 31 -- Max 9 -- 134
Note: Values in the table are the number of states.
14.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 14.6 shows the timing.
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 14.6 External Trigger Input Timing
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14. A/D Converter
14.5
Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 14.5. Table 14.5 A/D Converter Interrupt Source
Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible
14.6
Usage Notes
The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ANn Vref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref AVCC. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values.
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14. A/D Converter
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 14.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 14.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants.
AVCC
Vref Rin* 2 *1 *1 0.1 F 100 AN0 to AN7
AVSS
Notes:
Values are reference values. 1. 10 F 0.01 F
2. Rin: Input impedance
Figure 14.7 Example of Analog Input Protection Circuit
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14. A/D Converter
10 k AN0 to AN7 To A/D converter 20 pF
Note: Values are reference values.
Figure 14.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2355 Group A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 14.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 14.10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.
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14. A/D Converter
Digital output
111 110 101 100 011 010 001 000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 1024 1024
FS
Analog input voltage
Figure 14.9 A/D Conversion Precision Definitions (1)
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14. A/D Converter
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error
Actual A/D conversion characteristic FS Offset error Analog input voltage
Figure 14.10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2355 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted.
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14. A/D Converter
Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas.
H8/2355 Group Sensor output impedance to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF 20 pF
A/D converter equivalent circuit 10 k
Note: Values are reference values.
Figure 14.11 Example of Analog Input Circuit
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15. D/A Converter (Not Supported in H8S/2393)
Section 15 D/A Converter (Not Supported in H8S/2393)
15.1 Overview
The H8S/2355 and H8S/2353 include a two-channel D/A converter. 15.1.1 Features
D/A converter features are listed below * 8-bit resolution * Two output channels * Maximum conversion time of 10 s (with 20-pF load) * Output voltage of 0 V to Vref * D/A output hold function in software standby mode * Module stop mode can be set As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode.
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15. D/A Converter (Not Supported in H8S/2393)
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the D/A converter.
Module data bus
Bus interface DACR
Internal data bus
Vref AVCC
DADR0
8-bit DA1 D/A DA0 AVSS
Control circuit
Figure 15.1 Block Diagram of D/A Converter
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DADR1
15. D/A Converter (Not Supported in H8S/2393)
15.1.3
Pin Configuration
Table 15.1 summarizes the input and output pins of the D/A converter. Table 15.1 Pin Configuration
Pin Name Analog power pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog power source Analog ground and reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage
15.1.4
Register Configuration
Table 15.2 summarizes the registers of the D/A converter. Table 15.2 D/A Converter Registers
Name D/A data register 0 D/A data register 1 D/A control register Module stop control register Note: * Abbreviation DADR0 DADR1 DACR MSTPCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3FFF Address* H'FFA4 H'FFA5 H'FFA6 H'FF3C
Lower 16 bits of the address.
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15. D/A Converter (Not Supported in H8S/2393)
15.2
15.2.1
Bit
Register Descriptions
D/A Data Registers 0 and 1 (DADR0, DADR1)
: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Initial value: R/W :
DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 15.2.2
Bit
D/A Control Register (DACR)
: 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Initial value: R/W :
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel 1.
Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled Channel 1 D/A conversion is enabled; analog output DA1 is enabled (Initial value)
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Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output for channel 0.
Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value)
Bit 5--D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits.
Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 Legend: *: Don't care * Description Channel 0 and 1 D/A conversions disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversions enabled Channel 0 and 1 D/A conversions enabled
If the H8S/2355 Group enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0--Reserved: Read-only bits, always read as 1. It cannot be written to.
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15. D/A Converter (Not Supported in H8S/2393)
15.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. In the H8S/2355 and H8S/2353, when the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 19.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10--Module Stop (MSTP10): Specifies the D/A converter module stop mode.
Bit 10 MSTP10 0 1 Description D/A converter module stop mode cleared D/A converter module stop mode set (Initial value)
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15. D/A Converter (Not Supported in H8S/2393)
15.3
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 15.2 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents 256 x Vref
The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin.
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15. D/A Converter (Not Supported in H8S/2393)
DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle
Address
DADR0
Conversion data 1
Conversion data 2
DAOE0
DA0 High-impedance state tDCONV Legend: tDCONV: D/A conversion time
Conversion result 1 tDCONV
Conversion result 2
Figure 15.2 Example of D/A Converter Operation
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16. RAM
Section 16 RAM
16.1 Overview
The H8S/2355 and H8S/2393 have 4 kbytes of on-chip high-speed static RAM, and the H8S/2353 has 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 16.1.1 Block Diagram
Figure 16.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFEC00 H'FFEC02 H'FFEC04
H'FFEC01 H'FFEC03 H'FFEC05
H'FFFBFE
H'FFFBFF
Figure 16.1 Block Diagram of RAM (H8S/2355)
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16. RAM
16.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16.1 shows the address and initial value of SYSCR. Table 16.1 RAM Register
Name System control register Note: * Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FF39
Lower 16 bits of the address.
16.2
16.2.1
Bit
Register Descriptions
System Control Register (SYSCR)
: 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W
Initial value : R/W :
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
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16. RAM
16.3
Operation
When the RAME bit is set to 1, accesses to addresses H'FFEC00 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address.
16.4
Usage Note
DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0.
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16. RAM
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17. ROM
Section 17 ROM
17.1 Overview
The H8S/2355 has 128 kbytes of on-chip ROM (PROM or mask ROM). The H8S/2353 has 64 kbytes of on-chip mask ROM, and the H8S/2393 has 32 kbytes of on-chip mask ROM. The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. The PROM version of the H8S/2355 Group can be programmed with a general-purpose PROM programmer, by setting PROM mode. 17.1.1 Block Diagram
Figure 17.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000 H'000002
H'000001 H'000003
H'00FFFE H'010000 H'010002
H'00FFFF H'010001 H'010003 When EAE = 0
H'01FFFE
H'01FFFF
Figure 17.1 Block Diagram of ROM (H8S/2355)
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17. ROM
17.1.2
Register Configuration
The H8S/2355's on-chip ROM is controlled by BCRL. The register configuration is shown in table 17.1. Table 17.1 ROM Register
Initial Value Name Bus control register L Note: * Abbreviation BCRL R/W R/W Power-On Reset H'3C Manual Reset Retained Address* H'FED5
Lower 16 bits of the address.
17.2
17.2.1
Bit
Register Descriptions
Bus Control Register L (BCRL)
: 7 BRLE 0 R/W 6 -- 0 R/W 5 EAE 1 R/W 4 -- 1 R/W 3 -- 1 R/W 2 -- 1 R/W 1 -- 0 R/W 0 WAITE 0 R/W
Initial value : R/W :
Enabling or disabling of part of the H8S/2355's on-chip ROM area can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL). Bit 5--External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode.
Bit 5 EAE 0 1 Note: * Description Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2355) or a reserved area* (in the H8S/2353). Addresses H'010000 to H'01FFFF are external addresses (external expansion mode) or a reserved area* (single-chip mode). (Initial value) Reserved areas should not be accessed.
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17. ROM
17.3
Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. These settings are shown in table 17.2. In normal mode, a maximum of 56 kbytes of ROM can be used. Table 17.2 Operating Modes and ROM Area
Mode Pin Operating Mode Mode 1 Normal expanded mode with on-chip ROM disabled Mode 2 Normal expanded mode with on-chip ROM enabled Mode 3 Normal single-chip mode Mode 4 Advanced expanded mode with on-chip ROM disabled Mode 5 Advanced expanded mode with on-chip ROM disabled Mode 6 Advanced expanded mode with on-chip ROM enabled Mode 7 Advanced single-chip mode Note: * 1 1 0 MD2 0 MD1 0 1 MD0 1 0 1 0 1 0 0 1 1 0 1 Enabled* Enabled (64 kbytes) Enabled* Enabled (64 kbytes) -- Disabled BCRL EAE -- -- On-Chip ROM Disabled Enabled (56 kbytes)
128 kbytes in the H8S/2355, 64 kbytes in the H8S/2353, 32 kbytes in the H8S/2393 In H8/2355 modes 6 and 7, the on-chip ROM available after a power-on reset is the 64kbyte area comprising addresses H'000000 to H'00FFFF.
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17. ROM
17.4
17.4.1
PROM Mode
PROM Mode Setting
The PROM version of the H8S/2355 Group suspends its microcontroller functions when placed in PROM mode, enabling the on-chip PROM to be programmed. This programming can be done with a PROM programmer set up in the same way as for the HN27C101 EPROM (VPP = 12.5 V). Use of a socket adapter to convert from 120 or 128 pins to 32 pins enables programming with a commercial PROM programmer. Note that the PROM programmer should not be set to page mode as the H8S/2355 Group does not support page programming. Table 17.3 shows how PROM mode is selected. Table 17.3 Selecting PROM Mode
Pin Names MD2, MD1, MD0 STBY PA2, PA1 High Setting Low
17.4.2
Socket Adapter and Memory Map
Programs can be written and verified by attaching a socket adapter to convert from 120 or 128 pins to 32 pins to the PROM programmer. Table 17.4 gives ordering information for the socket adapter, and figure 17.2 shows the wiring of the socket adapter. Figure 17.3 shows the memory map in PROM mode.
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17. ROM
H8S/2355 Group
TFP-120 73 43 44 45 46 48 49 50 51 2 3 4 5 7 8 9 10 11 74 13 14 16 17 18 19 20 86 12 87 1, 33, 52, 76, 81 93 94 21 22 6, 15, 24, 38, 47, 59, 79, 104 103 75 113 114 115 FP-128 81 49 50 51 52 54 55 56 57 6 7 8 9 11 12 13 14 15 82 17 18 20 21 22 23 24 94 16 95 1, 39, 58, 84, 89 103 104 25 26 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100,114 113 83 123 124 125 AVSS STBY MD0 MD1 MD2 : Programming power supply (12.5 V) EO7 to EO0 : Data input/output EA16 to EA0 : Address input : Output enable OE : Chip enable CE : Program PGM Legend: VPP Pin RES PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 NMI PB2 PB3 PB4 PB5 PB6 PB7 PA0 PF2 PB1 PF1 VCC AVCC Vref PA1 PA2 VSS VSS 16
EPROM socket
Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC HN27C101 (32 Pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32
Note: Pins not shown in this figure should be left open.
Figure 17.2 Wiring of 120-Pin/32-Pin Socket Adapter
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17. ROM
Table 17.4 Socket Adapter
Microcontroller H8S/2355 Package 120 pin TQFP (TFP-120) 128 pin QFP (FP-128) Socket Adapter HS2655ESNS1H HS2655ESHS1H
Addresses in MCU mode H'000000
Addresses in PROM mode H'00000
On-chip PROM
H'01FFFF
H'1FFFF
Figure 17.3 Memory Map in PROM Mode
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17. ROM
17.5
17.5.1
Programming
Overview
Table 17.5 shows how to select the program, verify, and program-inhibit modes in PROM mode. Table 17.5 Mode Selection in PROM Mode
Pins Mode Program Verify Program-inhibit CE L L L L H H Legend: L: Low voltage level H: High voltage level VPP: VPP voltage level VCC: VCC voltage level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input
Programming and verification should be carried out using the same specifications as for the standard HN27C101 EPROM. However, do not set the PROM programmer to page mode does not support page programming. A PROM programmer that only supports page programming cannot be used. When choosing a PROM programmer, check that it supports high-speed programming in byte units. Always set addresses within the range H'00000 to H'1FFFF. 17.5.2 Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 17.4 shows the basic high-speed programming flowchart. Tables 17.6 and 17.7 list the electrical characteristics of the chip during programming. Figure 17.5 shows a timing chart.
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17. ROM
Start
Set programming/verification mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V
Address = 0
n=0
n+1n Yes No n < 25 Program with tPW = 0.2 ms 5 % Address + 1 address No Verification OK? Yes Program with tOPW = 0.2n ms
No Last address? Yes Set read mode VCC = 5.0 V 0.25 V VPP = VCC
Fail
No go
All addresses read? Go End
Figure 17.4 High-Speed Programming Flowchart
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17. ROM
Table 17.6 DC Characteristics in PROM Mode (When VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25 C 5 C)
Item Input high voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM EO7 to EO0, EA16 to EA0, OE, CE, PGM Symbol Min VIH 2.4 Typ -- Max VCC + 0.3 Test Unit Conditions V
Input low voltage
VIL
-0.3 --
0.8
V
Output high voltage EO7 to EO0 Output low voltage Input leakage current VCC current VPP current EO7 to EO0 EO7 to EO0, EA16 to EA0, OE, CE, PGM
VOH VOL | ILI |
2.4 -- --
-- -- --
-- 0.45 2
V V A
IOH = -200 A IOL = 1.6 mA Vin = 5.25 V/0.5 V
ICC IPP
-- --
-- --
40 40
mA mA
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17. ROM
Table 17.7 AC Characteristics in PROM Mode (When VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25 C 5 C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width PGM pulse width for overwrite programming VCC setup time CE setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF* tVPS tPW tOPW* tVCS tCES tOE
3 2
Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0
Typ -- -- -- -- -- -- -- 0.20 -- -- -- --
Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 150
Unit s s s s s ns s ms ms s s ns
Test Conditions Figure 17.5*
1
Notes: 1. Input pulse level: 0.8 V to 2.2 V Input rise time and fall time 20 ns Timing reference levels: Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined to be when output has reached the open state, and the output level can no longer be referenced. 3. tOPW is defined by the value shown in the flowchart.
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17. ROM
Program Address tAS Data tDS VPP VCC VPP VCC VCC +1 VCC tVPS tVCS Input data tDH tAH Output data tDF Verify
CE tCES PGM tPW OE tOPW* tOES tOE
Note: * tOPW is defined by the value shown in the flowchart.
Figure 17.5 PROM Programming/Verification Timing
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17. ROM
17.5.3
Programming Precautions
* Program using the specified voltages and timing. The programming voltage (VPP) in PROM mode is 12.5 V. If the PROM programmer is set to Renesas HN27C101 specifications, VPP will be 12.5 V. Applied voltages in excess of the specified values can permanently destroy the MCU. Be particularly careful about the PROM programmer's overshoot characteristics. * Before programming, check that the MCU is correctly mounted in the PROM programmer. Overcurrent damage to the MCU can result if the index marks on the PROM programmer, socket adapter, and MCU are not correctly aligned. * Do not touch the socket adapter or MCU while programming. Touching either of these can cause contact faults and programming errors. * The MCU cannot be programmed in page programming mode. Select the programming mode carefully. * The size of the H8S/2355 PROM is 128 kbytes. Always set addresses within the range H'00000 to H'1FFFF. During programming, write H'FF to unused addresses to avoid verification errors.
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17. ROM
17.5.4
Reliability of Programmed Data
An effective way to assure the data retention characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM cells prone to early failure. Figure 17.6 shows the recommended screening procedure.
Program chip and verify data
Bake chip for 24 to 48 hours at 125C to 150C with power off
Read and check program
Mount
Figure 17.6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is being used, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
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17. ROM
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18. Clock Pulse Generator
Section 18 Clock Pulse Generator
18.1 Overview
The H8S/2355 Group has a built-in clock pulse generator (CPG) that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit. 18.1.1 Block Diagram
Figure 18.1 shows a block diagram of the clock pulse generator.
SCKCR SCK2 to SCK0 Mediumspeed divider EXTAL Oscillator XTAL
Duty adjustment circuit
/2 to /32 Bus master clock selection circuit
System clock to pin
Internal clock to supporting modules
Bus master clock to CPU and DTC
Figure 18.1 Block Diagram of Clock Pulse Generator 18.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 18.1 shows the register configuration. Table 18.1 Clock Pulse Generator Register
Name System clock control register Note: * Abbreviation SCKCR R/W R/W Initial Value H'00 Address* H'FF3A
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18. Clock Pulse Generator
18.2
18.2.1
Bit
Register Descriptions
System Clock Control Register (SCKCR)
: 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W
Initial value: R/W :
SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Output Disable (PSTOP): Controls output.
Description Bit 7 PSTOP 0 1 Normal Operation output (initial value) Fixed high Sleep Mode output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance
Bit 6--Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3--Reserved: Read-only bits, always read as 0.
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18. Clock Pulse Generator
Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value)
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18. Clock Pulse Generator
18.3
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 18.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance Rd according to table 18.2. An AT-cut parallel-resonance crystal should be used.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF
Figure 18.2 Connection of Crystal Resonator (Example) Table 18.2 Damping Resistance Value
Frequency (MHz) Rd () 2 1k 4 500 8 200 12 0 16 0 20 0
Crystal Resonator: Figure 18.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.3 and the same resonance frequency as the system clock ().
CL L XTAL Rs EXTAL AT-cut parallel-resonance type
C0
Figure 18.3 Crystal Resonator Equivalent Circuit
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18. Clock Pulse Generator
Table 18.3 Crystal Resonator Parameters
Frequency (MHz) RS max () C0 max (pF) 2 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7
Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 18.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins.
Avoid CL2 Signal A Signal B H8S/2355 XTAL EXTAL CL1
Figure 18.4 Example of Incorrect Board Design
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18. Clock Pulse Generator
18.3.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode.
EXTAL XTAL Open
External clock input
(a) XTAL pin left open
EXTAL XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 18.5 External Clock Input (Examples) External Clock: The external clock signal should have the same frequency as the system clock (). Table 18.4 and figure 18.6 show the input conditions for the external clock.
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18. Clock Pulse Generator
Table 18.4 External Clock Input Conditions
VCC = 2.7 V to 5.5 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Clock high pulse width level Symbol tEXL tEXH tEXr tEXf tCL tCH Min 40 40 -- -- 0.4 80 0.4 80 Max -- -- 10 10 0.6 -- 0.6 -- VCC = 5.0 V 10 % Min 20 20 -- -- 0.4 80 0.4 80 Max -- -- 5 5 0.6 -- 0.6 -- Unit ns ns ns ns tcyc ns tcyc ns 5 MHz < 5 MHz 5 MHz < 5 MHz Figure 20.4 Test Conditions Figure 18.6
tEXH
tEXL
EXTAL
VCC x 0.5
tEXr
tEXf
Figure 18.6 External Clock Input Timing
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18. Clock Pulse Generator
18.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock ().
18.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32.
18.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock () or one of the medium-speed clocks (/2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR.
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19. Power-Down Modes
Section 19 Power-Down Modes
19.1 Overview
In addition to the normal program execution state, the H8S/2355 Group has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2355 Group operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode Of these, (2) to (6) are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2355 Group is in high-speed mode. Table 19.1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode.
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19. Power-Down Modes
Table 19.1 Operating Modes
Operating Mode High speed mode Transition Condition Control register Clearing Condition Control register Control register Interrupt Control register External interrupt Pin CPU Oscillator Functions Functions High speed Registers Functions High speed Modules Registers Functions I/O Ports High speed High speed
MediumControl speed mode register Sleep mode Instruction Module stop Control mode register Software standby mode Hardware standby mode Instruction
Medium Functions speed Halted Retained
High/ Functions medium speed *1 High speed Halted Functions Retained/ reset *2 Retained/ reset *2 Reset
Functions Functions
High speed Retained
High/ Functions medium speed Halted Retained
Halted
Halted
Retained
Pin
Halted
Halted
Undefined
Halted
High impedance
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI and A/D converter are reset, and other on-chip supporting modules retain their state.
19.1.1
Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 19.2 summarizes these registers. Table 19.2 Power-Down Mode Registers
Name Standby control register System clock control register Module stop control register H Module stop control register L Note: * Abbreviation SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'3F H'FF Address* H'FF38 H'FF3A H'FF3C H'FF3D
Lower 16 bits of the address.
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19. Power-Down Modes
19.2
19.2.1
Bit
Register Descriptions
Standby Control Register (SBYCR)
: 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 R/W
Initial value : R/W :
SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it.
Bit 7 SSBY 0 1 Description Transition to sleep mode after execution of SLEEP instruction (Initial value)
Transition to software standby mode after execution of SLEEP instruction
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19. Power-Down Modes
Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 19.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made.
Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Initial value)
Bit 3--Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR) is retained or set to the high-impedance state in software standby mode.
Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value)
Bits 2 and 1--Reserved: Read-only bits, always read as 0. Bit 0--Reserved: This bit can be read or written to, but only 0 should be written.
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19. Power-Down Modes
19.2.2
Bit
System Clock Control Register (SCKCR)
: 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W
Initial value : R/W :
SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Output Disable (PSTOP): Controls output.
Description Bit 7 PSTOP 0 1 Normal Operating Mode output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance
Sleep Mode output Fixed high
Bits 6--Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value)
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19. Power-Down Modes
19.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit
:
15 0
14 0
13 1
12 1
11 1
Initial value : R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0--Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 19.3 for the method of selecting on-chip supporting modules.
Bits 15 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode cleared Module stop mode set
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19. Power-Down Modes
19.3
Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 19.1 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode , supporting module clock Bus master clock
Internal address bus Internal write signal
SCKCR
SCKCR
Figure 19.1 Medium-Speed Mode Transition and Clearance Timing
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19. Power-Down Modes
19.4
Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode.
19.5
19.5.1
Module Stop Mode
Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 19.3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D converter are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. If a transition is made to sleep mode when all modules are stopped (MSTPCR = H'FFFF), or modules other than the 8-bit timers are stopped (MSTPCR = H'EFFF), operation of the bus controller and I/O ports is also halted, enabling current dissipation to be further reduced.
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19. Power-Down Modes
Table 19.3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register MSTPCRH Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module -- Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer -- D/A converter* A/D converter -- Serial communication interface (SCI) channel 2 Serial communication interface (SCI) channel 1 Serial communication interface (SCI) channel 0 -- -- -- -- --
Note: Bits 15, 11, 8, and 4 to 0 can be read or written to, but do not affect operation. * In the H8S/2393 bit 10 can be read and written to but has no effect on operation, as a D/A converter is not supported.
19.5.2
Usage Notes
DTC Module Stop: Depending on the operating status of the DTC, the MSTP14 bit may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU.
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19. Power-Down Modes
19.6
19.6.1
Software Standby Mode
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 19.6.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire H8S/2355 Group chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2355 Group chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode.
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19. Power-Down Modes
19.6.3
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 19.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 19.4 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 4.1 8.2 ms
8.2 16.4
10.9 16.4 32.8
10.9 13.1 16.4 21.8 32.8 65.5
13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 2.7 -- 4.0 -- 8.0 -- s
: Recommended time setting
Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended. 19.6.4 Software Standby Mode Application Example
Figure 19.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
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19. Power-Down Modes
Oscillator
NMI
NMIEG
SSBY
NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction
Oscillation stabilization time tOSC2
NMI exception handling
Figure 19.2 Software Standby Mode Application Example 19.6.5 Usage Notes
I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period.
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19. Power-Down Modes
19.7
19.7.1
Hardware Standby Mode
Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2355 Group is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 19.7.2 Hardware Standby Mode Timing
Figure 19.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
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19. Power-Down Modes
Oscillator
RES
STBY
Oscillation stabilization time
Reset exception handling
Figure 19.3 Hardware Standby Mode Timing (Example)
19.8
Clock Output Disabling Function
Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 19.5 shows the state of the pin in each processing state. Table 19.5 Pin State in Each Processing State
DDR PSTOP Hardware standby mode Software standby mode Sleep mode Normal operating state 0 -- High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high output output 1 High impedance Fixed high Fixed high Fixed high
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20. Electrical Characteristics
Section 20 Electrical Characteristics
20.1 Absolute Maximum Ratings
Table 20.1 lists the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings
Item Power supply voltage Programming voltage Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC VPP Vin Vin Vref AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to +13.5 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature -55 to +125 Unit V V V V V V V C C C
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
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20. Electrical Characteristics
20.2
DC Characteristics
Table 20.2 lists the DC characteristics. Table 20.3 lists the permissible output currents. Table 20.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10 %, AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V* , Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
1
Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P67, PA4 to PA7 RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high voltage Output low voltage Input leakage current
Symbol VT VT
- + + -
Min 1.0 -- 0.4 VCC - 0.7
Typ -- -- -- --
Max -- VCC x 0.7 -- VCC + 0.3
Unit V V V V
Test Conditions
VT - VT VIH
VCC x 0.7 2.0
-- --
VCC + 0.3 VCC + 0.3
V V
2.0 VIL -0.3 -0.3
-- -- --
AVCC + 0.3 V 0.5 0.8 V V
All output pins VOH All output pins VOL Ports 1, A to C RES STBY, NMI, MD2 to MD0 Port 4 | Iin |
VCC - 0.5 3.5 -- -- -- -- --
-- -- -- -- -- -- --
-- -- 0.4 1.0 10.0 1.0 1.0
V V V V A A A
IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 10 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V
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20. Electrical Characteristics Item Three-state leakage current (off state) Ports 1 to 3, 5, 6, A to G Symbol ITSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V
MOS input Port A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current 2 dissipation* Normal operation Sleep mode Standby 3 mode* Analog power During A/D supply current and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage
-IP Cin
50 -- -- --
-- -- -- --
300 80 50 15
A pF pF pF
Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25 C
ICC*
4
-- -- -- --
60 89 (5.0 V) 40 73 (5.0 V) 0.01 -- 5.0 20
mA mA A
f = 20 MHz f = 20 MHz Ta 50 C 50 C < Ta
AlCC
--
0.8 2.0 (5.0 V) 0.01 5.0
mA
-- AlCC --
A mA
1.9 3.0 (5.0 V) 0.01 -- 5.0 --
-- VRAM 2.0
A V
Notes: 1. If the A/D and D/A converters are not used,do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 0.80 (mA/(MHz x V)) x VCC x f [normal mode] ICC max = 1.0 (mA) + 0.65 (mA/(MHz x V)) x VCC x f [sleep mode]
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20. Electrical Characteristics
Table 20.2 DC Characteristics (2) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V* , Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P67, PA4 to PA7 RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high voltage Output low voltage All output pins VOH All output pins VOL Ports 1, A to C VIL Symbol VT- VT+ VIH Min VCC x 0.2 -- VCC x 0.9 Typ -- -- Max -- VCC x 0.7 -- VCC + 0.3 Unit V V V V Test Conditions
1
VT+ - VT- VCC x 0.07 -- --
VCC x 0.7 VCC x 0.7
-- --
VCC + 0.3 VCC + 0.3
V V
VCC x 0.7 -0.3 -0.3
-- -- --
AVCC + 0.3 V VCC x 0.1 VCC x 0.2 0.8 V V VCC < 4.0 V VCC = 4.0 to 5.5 V
VCC - 0.5 VCC - 1.0 -- --
-- -- -- --
-- -- 0.4 1.0
V V V V
IOH = -200 A IOH = -1 mA IOL = 1.6 mA VCC 4 V IOL = 5 mA 4.0 < VCC 5.5 V IOL = 10 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V
Input leakage current
RES STBY, NMI, MD2 to MD0 Port 4
| Iin |
-- -- --
-- -- --
10.0 1.0 1.0
A A A
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20. Electrical Characteristics Item Three-state leakage current (off state) Ports 1 to 3, 5, 6, A to G Symbol ITSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V
MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current 2 dissipation* Normal operation Sleep mode Standby 3 mode* Analog power During A/D supply current and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage
-IP Cin
10 -- -- --
-- -- -- --
300 80 50 15
A pF pF pF
VCC = 2.7 V to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25 C
ICC*
4
-- -- -- --
18 45 (3.0 V) 11 37 (3.0 V) 0.01 -- 5.0 20
mA mA A
f = 10 MHz f = 10 MHz Ta 50 C 50 C < Ta
AlCC
--
0.2 2.0 (3.0 V) 0.01 5.0
mA
-- AlCC --
A mA
1.2 3.0 (3.0 V) 0.01 -- 5.0 --
-- VRAM 2.0
A V
Notes: 1. If the A/D and D/A converters are not used,do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 0.80 (mA/(MHz x V)) x VCC x f [normal mode] ICC max = 1.0 (mA) + 0.65 (mA/(MHz x V)) x VCC x f [sleep mode]
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20. Electrical Characteristics
Table 20.2 DC Characteristics (3) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V* , Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P67, PA4 to PA7 RES, STBY, NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high voltage Output low voltage All output pins VOH All output pins VOL Ports 1, A to C VIL Symbol VT VT
- +
1
Min VCC x 0.2 -- VCC x 0.9
Typ -- --
Max -- VCC x 0.7 -- VCC + 0.3
Unit V V V V
Test Conditions
VT - VT- VCC x 0.07 --
+
VIH
--
VCC x 0.7 VCC x 0.7
-- --
VCC + 0.3 VCC + 0.3
V V
VCC x 0.7 -0.3 -0.3
-- -- --
AVCC + 0.3 V VCC x 0.1 VCC x 0.2 V V VCC < 4.0 V
0.8 VCC - 0.5 VCC - 1.0 -- -- -- -- -- -- -- -- 0.4 1.0 V V V V
VCC = 4.0 to 5.5 V IOH = -200 A IOH = -1 mA IOL = 1.6 mA VCC 4 V IOL = 5 mA 4.0 < VCC 5.5 V IOL = 10 mA Vin = 0.5 to VCC - 0.5V Vin = 0.5 to AVCC - 0.5V
Input leakage current
RES STBY, NMI, MD2 to MD0 Port 4
| Iin |
-- -- --
-- -- --
10.0 1.0 1.0
A A A
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20. Electrical Characteristics Item Three-state leakage current (off state) Ports 1 to 3, 5, 6, A to G Symbol ITSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V
MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current 2 dissipation* Normal operation Sleep mode Standby 3 mode* Analog power During A/D supply current and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage
-IP Cin
10 -- -- --
-- -- -- --
300 80 50 15
A pF pF pF
VCC = 3.0 V to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25 C
ICC*
4
-- -- -- --
25 58 (3.3 V) 16 48 (3.3 V) 0.01 -- 5.0 20.0
mA mA A
f = 13 MHz f = 13 MHz Ta 50 C 50 C < Ta
AlCC
--
0.2 2.0 (3.3 V) 0.01 5.0
mA
-- AlCC --
A mA
1.2 3.0 (3.3 V) 0.01 -- 5.0 --
-- VRAM 2.0
A V
Notes: 1. If the A/D and D/A converters are not used,do not leave the AVCC, AVSS, and Vref pins open. Connect AVCC and Vref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 0.80 (mA/(MHz x V)) x VCC x f [normal mode] ICC max = 1.0 (mA) + 0.65 (mA/(MHz x V)) x VCC x f [sleep mode]
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20. Electrical Characteristics
Table 20.3 Permissible Output Currents Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, A to C Other output pins Total of 32 pins including port 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min -- -- -- Typ -- -- -- Max 10 2.0 80 Unit mA mA mA
--
--
120
mA
-- --
-- --
2.0 40
mA mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 20.3. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 20.1 and 20.2.
H8S/2355 Group
2 k Port
Darlington Pair
Figure 20.1 Darlington Pair Drive Circuit (Example)
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20. Electrical Characteristics
H8S/2355 Group
600 Ports 1, A to C LED
Figure 20.2 LED Drive Circuit (Example)
20.3
AC Characteristics
Figure 20.3 show, the test conditions for the AC characteristics.
5V RL LSI output pin C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 k RH = 12 k I/O timing test levels * Low level: 0.8 V * High level: 2.0 V
C
RH
Figure 20.3 Output Load Circuit
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20. Electrical Characteristics
20.3.1
Clock Timing
Table 20.4 lists the clock timing Table 20.4 Clock Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition B: VCC = 5.0 V 10 %, AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition C: (mask ROM version only) VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Condition A Condition B Condition C Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Symbol Min tcyc tCH tCL tCr tCf tOSC1 100 35 35 -- -- 20 8 500 Max 500 -- -- 15 15 -- -- -- Min 50 20 20 -- -- 10 8 500 Max 500 -- -- 5 5 -- -- -- Min 76 23 23 -- -- 20 20 500 Max 500 -- -- 15 15 -- -- -- Test Unit Conditions ns ns ns ns ns ms ms s Figure 20.5 Figure 19.2 Figure 20.5 Figure 20.4
Clock oscillator setting time tOSC2 in software standby (crystal) External clock output stabilization delay time tDEXT
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20. Electrical Characteristics
tcyc tCH tCL tCr tCf
Figure 20.4 System Clock Timing
EXTAL tDEXT VCC tDEXT
STBY
NMI tOSC1 tOSC1
RES
Figure 20.5 Oscillator Settling Timing
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20. Electrical Characteristics
20.3.2
Control Signal Timing
Table 20.5 lists the control signal timing. Table 20.5 Control Signal Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition B: VCC = 5.0 V 10 %, AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition C: (mask ROM version only) VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Condition A Condition B Condition C Item RES setup time RES pulse width NMI reset setup time NMI reset hold time NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol Min tRESS tRESW tNMIRS tNMIRH tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW 200 20 250 200 250 10 200 250 10 200 Max -- -- -- -- -- -- -- -- -- -- Min 200 20 200 200 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- -- -- Min 200 20 250 200 250 10 200 250 10 200 Max -- -- -- -- -- -- -- -- -- -- Test Unit Conditions ns tcyc ns ns ns ns ns ns ns ns Figure 20.7 Figure 20.6
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20. Electrical Characteristics
tRESS RES tRESW tNMIRS NMI tRESS
tNMIRH
Figure 20.6 Reset Input Timing
tNMIS NMI tNMIW tNMIH
IRQi (i = 0 to 2) tIRQS IRQ Edge input tIRQS IRQ Level input
tIRQW tIRQH
Figure 20.7 Interrupt Input Timing
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20. Electrical Characteristics
20.3.3
Bus Timing
Table 20.6 lists the bus timing. Table 20.6 Bus Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition B: VCC = 5.0 V 10 %, AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition C: (mask ROM version only) VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Condition A Item Address delay time Address setup time Address hold time CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Symbol Min tAD tAS tAH tCSD1 tASD tRSD1 tRSD2 -- Max 40 Condition B Min -- Max 20 Condition C Min -- Max 40 Test Unit Conditions ns ns ns ns ns ns ns ns ns Figure 20.8 to Figure 20.12
0.5 x -- tcyc - 30 0.5 x -- tcyc - 20 -- -- -- -- 30 0 -- -- -- 40 40 40 40 -- -- 1.0 x tcyc - 50 1.5 x tcyc - 50 2.0 x tcyc - 50
0.5 x -- tcyc - 15 0.5 x -- tcyc - 10 -- -- -- -- 15 0 -- -- -- 20 20 20 20 -- -- 1.0 x tcyc - 25 1.5 x tcyc - 25 2.0 x tcyc - 25
0.5 x -- tcyc - 30 0.5 x -- tcyc - 20 -- -- -- -- 30 0 -- -- -- 40 40 40 40 -- --
Read data setup time tRDS Read data hold time Read data access time1 Read data access time2 Read data access time3 tRDH tACC1 tACC2 tACC3
1.0 x ns tcyc - 50 1.5 x ns tcyc - 50 2.0 x ns tcyc - 50
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20. Electrical Characteristics
Condition A Item Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Symbol Min tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 -- -- -- -- Max 2.5 x tcyc - 50 3.0 x tcyc - 50 40 40 Condition B Min -- -- -- -- Max 2.5 x tcyc - 25 3.0 x tcyc - 25 20 20 Condition C Min -- -- -- -- Max Test Unit Conditions Figure 20.8 to Figure 20.12
2.5 x ns tcyc - 50 3.0 x ns tcyc - 50 40 40 ns ns ns ns ns ns ns ns ns ns ns ns
1.0 x -- tcyc - 40 1.5 x -- tcyc - 40 -- 60
1.0 x -- tcyc - 20 1.5 x -- tcyc - 20 -- 30
1.0 x -- tcyc - 40 1.5 x -- tcyc - 40 -- 60
Write data delay time tWDD Write data setup time tWDS Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time tWDH tWTS tWTH tBRQS tBACD tBZD
0.5 x -- tcyc - 40 0.5 x -- tcyc - 20 60 10 60 -- -- -- -- -- 30 100
0.5 x -- tcyc - 20 0.5 x -- tcyc - 10 30 5 30 -- -- -- -- -- 15 50
0.5 x -- tcyc - 33 0.5 x -- tcyc - 20 60 10 60 -- -- -- -- -- 30 75
Figure 20.10
Figure 20.13
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20. Electrical Characteristics
T1 tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tRSD2 tASD tAS tAH T2
tRSD1 RD (read) tAS
tACC2
tACC3 D15 to D0 (read)
tRDS tRDH
tWRD2 HWR, LWR (write)
tWRD2 tAH
tAS tWDD tWSW1
tWDH
D15 to D0 (write)
Figure 20.8 Basic Bus Timing (Two-State Access)
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20. Electrical Characteristics
T1 T2 T3
tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tASD tAS tAH
tRSD1 RD (read) tAS
tACC4
tRSD2
tACC5 D15 to D0 (read)
tRDS tRDH
tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2
tWRD2 tAH tWDH
Figure 20.9 Basic Bus Timing (Three-State Access)
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20. Electrical Characteristics
T1 T2 TW T3
A23 to A0
CS7 to CS0
AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH
Figure 20.10 Basic Bus Timing (Three-State Access with One Wait State)
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20. Electrical Characteristics
T1 T2 or T3 T1 T2
tAD A23 to A0 tAS CS7 to CS0 tASD AS tASD tAH
tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH
Figure 20.11 Burst ROM Access Timing (Two-State Access)
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20. Electrical Characteristics
T1 T2 or T3 T1
tAD A23 to A0
CS7 to CS0
AS
tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH
Figure 20.12 Burst ROM Access Timing (One-State Access)
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20. Electrical Characteristics
tBRQS
tBRQS BREQ tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR
tBACD
tBZD
Figure 20.13 External Bus Release Timing
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20. Electrical Characteristics
20.3.4
Timing of On-Chip Supporting Modules
Table 20.7 lists the timing of on-chip supporting modules. Table 20.7 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition B: VCC = 5.0 V 10 %, AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition C: (mask ROM version only) VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Condition A Item I/O port Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL Min -- 50 50 -- 50 50 1.5 2.5 Max 100 -- -- 100 -- -- -- -- Condition B Min -- 30 30 -- 30 30 1.5 2.5 Max 50 -- -- 50 -- -- -- -- Condition C Min -- 50 50 -- 50 50 1.5 2.5 Max 75 -- -- 75 -- -- -- -- ns tcyc Figure 20.16 ns Figure 20.15 Test Unit Conditions ns Figure 20.14
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20. Electrical Characteristics
Condition A Item TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width WDT SCI Single edge Both edges Symbol tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD Min -- 50 50 1.5 2.5 -- 4 6 tSCKW tSCKr tSCKf tTXD 0.4 -- -- -- 100 100 50 Max 100 -- -- -- -- 100 -- -- 0.6 1.5 1.5 100 -- -- -- Condition B Min -- 30 30 1.5 2.5 -- 4 6 0.4 -- -- -- 50 50 30 Max 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- Condition C Min -- 50 50 1.5 2.5 -- 4 6 0.4 -- -- -- 75 75 50 Max 75 -- -- -- -- 75 -- -- 0.6 1.5 1.5 75 -- -- -- ns ns ns ns Figure 20.23 Figure 20.22 tScyc tcyc ns tcyc Figure 20.20 Figure 20.21 Test Unit Conditions ns ns ns tcyc Figure 20.17 Figure 20.19 Figure 20.18 Figure 20.18
Overflow output delay time Input clock cycle
Asynchro- tScyc nous Synchronous
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time
Receive data setup tRXS time (synchronous) Receive data hold tRXH time (synchronous) A/D Trigger input setup converter time tTRGS
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20. Electrical Characteristics
T1 tPRS Ports 1 to 6, A to G (read) tPWD Ports 1 to 3, 5, 6, A to G (write) tPRH T2
Figure 20.14 I/O Port Input/Output Timing
tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 20.15 TPU Input/Output Timing
tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS
Figure 20.16 TPU Clock Input Timing
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20. Electrical Characteristics
tTMOD TMO0, TMO1
Figure 20.17 8-Bit Timer Output Timing
tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS
Figure 20.18 8-Bit Timer Clock Input Timing
tTMRS TMRI0, TMRI1
Figure 20.19 8-Bit Timer Reset Input Timing
tWOVD WDTOVF
tWOVD
Figure 20.20 WDT Output Timing
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20. Electrical Characteristics
tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf
Figure 20.21 SCK Clock Input Timing
SCK0 to SCK2 tTXD TxD0 to TxD2 transit data tRXS RxD0 to RxD2 receive data tRXH
Figure 20.22 SCI Input/Output Timing (Clock Synchronous Mode)
tTRGS ADTRG
Figure 20.23 A/D Converter External Trigger Input Timing
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20. Electrical Characteristics
20.4
A/D Conversion Characteristics
Table 20.8 lists the A/D conversion characteristics. Table 20.8 A/D Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition C: (mask ROM version only) VCC = AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Notes: 1. 2. 3. 4. 5. Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 13.4 20 10* 5*
2 1
Condition B Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 6.7 20 10* 5*
4 3
Condition C Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 10.4 20 10* 5*
5 1
Unit bits s pF k
7.5 7.5 7.5 0.5 8.0
3.5 3.5 3.5 0.5 4.0
7.5 7.5 7.5 0.5 8.0
LSB LSB LSB LSB LSB
4.0 V AVCC 5.5 V 2.7 V AVCC < 4.0 V 12 MHz > 12 MHz 3.0 V AVCC < 4.0 V
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20. Electrical Characteristics
20.5
D/A Convervion Characteristics
Table 20.9 lists the D/A conversion characteristics. Table 20.9 D/A Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V 10 %, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 to 20 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications) Condition C: (mask ROM version only) VCC = AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 2 to 13 MHz, Ta = -20 to +75 C (regular specifications), Ta = -40 to +85 C (wide-range specifications)
Condition A Item Resolution Conversion time Condition B Condition C
Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions 8 -- 8 -- 8 10 8 -- 8 -- 8 10 8 -- 8 -- 8 10 bit s 20-pF capacitive load
Absolute accuracy -- --
2.0 3.0 -- -- 2.0 --
1.0 1.5 -- -- 1.0 --
2.0 3.0 LSB 2-M resistive load -- 2.0 LSB 4-M resistive load
20.6
Usage Note
Although both the ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT version, a similar evaluation should also be performed using the mask ROM version.
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Appendix A. Instruction Set
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 General register (destination)* General register (source)*
1 1 1
General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register)* Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length
2
Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2355 Group.
Rev.4.00 Feb. 13, 2007 Page 613 of 846 REJ09B0354-0400
Appendix A. Instruction Set
Condition Code Notation
Symbol Changes according to the result of instruction * 0 1 -- Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction
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Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
--
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa
Mnemonic B2 B B B B B B B B B B B B B B B W4 W W 2 2 6 4 2 Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 Rs16Rd16 @ERsRd16 2 8 Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd 4 Rs8@(d:16,ERd) 2 Rs8@ERd 6 @aa:32Rd8 4 @aa:16Rd8 2 @aa:8Rd8 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 @ERsRd8,ERs32+1ERs32 ---- 8 @(d:32,ERs)Rd8 ---- 4 @(d:16,ERs)Rd8 ---- 2 @ERsRd8 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- ---- 0-- 2 Rs8Rd8 ---- 0-- #xx:8Rd8 ---- 0-- 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2
Operation
I H N Z V C Normal Advanced
MOV
MOV.B #xx:8,Rd
Table A.1 Instruction Set
MOV.B Rs,Rd
MOV.B @ERs,Rd
(1) Data Transfer Instructions
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 615 of 846 REJ09B0354-0400
MOV.W @ERs,Rd
MOV.W Rs,Rd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic W W W W W W W W W W W L6 L L L L L L L 4 6 8 10 6 4 2 6 4 Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 @aa:32ERd32 2 8 Rs16@(d:32,ERd) 4 Rs16@(d:16,ERd) 2 Rs16@ERd 6 @aa:32Rd16 4 @aa:16Rd16 ---- ---- ---- ---- ---- 2 @ERsRd16,ERs32+2ERs32 -- -- 8 @(d:32,ERs)Rd16 ---- 4 @(d:16,ERs)Rd16 ----
Operation
I H N Z V C Normal Advanced 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6
MOV
MOV.W @(d:16,ERs),Rd
Appendix A. Instruction Set
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
ERd32-2ERd32,Rs16@ERd -- --
MOV.L @aa:32,ERd
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MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic L 6 10 4 6 8 2 4 2 4 4 SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeated for each register restored L 4 (SP-4SP,ERn32@SP) Repeated for each register saved Cannot be used in the H8S/2355 Group Cannot be used in the H8S/2355 Group @SPRn16,SP+2SP @SPERn32,SP+4SP ERs32@aa:32 ERs32@aa:16 ERs32@(d:32,ERd) ---- ERd32-4ERd32,ERs32@ERd -- -- ---- ---- ---- ---- ---- ---- ERs32@(d:16,ERd) ---- 4 ERs32@ERd ----
Operation
I H N Z V C Normal Advanced 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- ------------ 4 5 7 5 5 6 3 5 3 5 7/9/11 [1]
MOV
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd) L
MOV.L ERs,@(d:32,ERd) L L L L W L W L L
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
POP
POP.W Rn
POP.L ERn
PUSH.L ERn
LDM
LDM @SP+,(ERm-ERn)
STM
STM (ERm-ERn),@-SP
------------
PUSH
PUSH.W Rn
7/9/11 [1]
MOVFPE
MOVFPE @aa:16,Rd
[2] [2]
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MOVTPE
MOVTPE Rs,@aa:16
Appendix A. Instruction Set
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B2 B W4 W L6 L B2 B L L L B W W L L B B W4 2 2 2 2 2 2 2 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjustRd8 Rd8-Rs8Rd8 Rd16-#xx:16Rd16 2 ERd32+4ERd32 2 ERd32+2ERd32 2 ERd32+1ERd32 2 Rd8+Rs8+CRd8 Rd8+#xx:8+CRd8 2 ERd32+ERs32ERd32 -- -- -- [4] ERd32+#xx:32ERd32 -- [4] 2 Rd16+Rs16Rd16 -- [3] Rd16+#xx:16Rd16 -- [3] 2 Rd8+Rs8Rd8 -- Rd8+#xx:8Rd8 --
Operation
I H N Z V C Normal Advanced

ADD
ADD.B #xx:8,Rd
1 1 2 1 3 1
Appendix A. Instruction Set
(2) Arithmetic Instructions
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd

[5]
ADDX Rs,Rd
[5]
SUB
SUB.B Rs,Rd
--

SUB.W #xx:16,Rd
-- [3]

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1 1 ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- --* * 1 1 1 1 1 1 1 1 1 1 2
ADD.L ERs,ERd
ADDX
ADDX #xx:8,Rd
ADDS
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
INC
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
DAA
DAA Rd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic W L6 L B2 B L L L B W W L L B B W 2 2 2 2 2 2 2 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjustRd8 2 Rd8-1Rd8 2 ERd32-4ERd32 2 ERd32-2ERd32 2 ERd32-1ERd32 2 Rd8-Rs8-CRd8 Rd8-#xx:8-CRd8 -- -- 2 ERd32-ERs32ERd32 -- [4] ERd32-#xx:32ERd32 -- [4] 2 Rd16-Rs16Rd16 -- [3]
Operation
I H N Z V C Normal Advanced 1 3 1 [5] [5] 1 1 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- 1 1 1 1 1 1 1 1 1
SUB
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBX Rs,Rd
SUBS
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
DEC
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DAS
DAS Rd
MULXU
MULXU.B Rs,Rd
Rd8xRs8Rd16 (unsigned multiplication) -- -- -- -- -- -- Rd16xRs16ERd32 (unsigned multiplication) ------------

DEC.L #2,ERd

SUBX
SUBX #xx:8,Rd
12 20
MULXU.W Rs,ERd
MULXS.W Rs,ERd
W
4
Rd16xRs16ERd32 (signed multiplication)
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 619 of 846 REJ09B0354-0400
B 4
----

Rd8xRs8Rd16 (signed multiplication) ----
MULXS
MULXS.B Rs,Rd
---- ----
13 21
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
--
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa
Mnemonic B RdL: quotient) (unsigned division) W Rd: quotient) (unsigned division) B RdL: quotient) (signed division) W Rd8-#xx:8 2 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 2 2 2 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 0-ERd32ERd32 0( of Rd16) 0( of ERd32) Rd8-Rs8 4 4 2 2
Operation
I H N Z V C Normal Advanced 12
Appendix A. Instruction Set
DIVXU
DIVXU.B Rs,Rd
Rd16/Rs8Rd16 (RdH: remainder, -- -- [6] [7] -- --
DIVXU.W Rs,ERd
ERd32/Rs16ERd32 (Ed: remainder, -- -- [6] [7] -- --
20
NEG.L ERd W L
L
--

EXTU.L ERd
---- 0

Rev.4.00 Feb. 13, 2007 Page 620 of 846 REJ09B0354-0400
Rd16/Rs8Rd16 (RdH: remainder, -- -- [8] [7] -- -- 13 ERd32/Rs16ERd32 (Ed: remainder, -- -- [8] [7] -- -- Rd: quotient) (signed division) B2 B W4 W L6 L B W -- -- 1 1 -- [3] 2 -- [3] 1 -- [4] 3 -- [4] -- -- 1 1 1 1 ---- 0 0-- 0-- 1 1 21
DIVXS
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG
NEG.B Rd
NEG.W Rd
EXTU
EXTU.W Rd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic
Operation
I H N Z V C Normal Advanced
( of Rd16)
( of ERd32)
( of @ERd) Cannot be used in the H8S/2355 Group [2]
MAC
MAC @ERn+, @ERm+
CLRMAC
CLRMAC
LDMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
STMAC
STMAC MACH,ERd
STMAC MACL,ERd

TAS B @ERd-0CCR set, (1) 4
TAS @ERd
----

EXTS.L ERd ( of ERd32)
L
2
----

EXTS ( of Rd16) ----
EXTS.W Rd
W
2
0--
1
0--
1
0--
4
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 621 of 846 REJ09B0354-0400
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 L B W L 2 2 2 4 2 2 4 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8Rd8 Rd16Rd16 ERd32ERd32 Rd16#xx:16Rd16 2 Rd8Rs8Rd8 Rd8#xx:8Rd8 4 ERd32ERs32ERd32 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ERd32#xx:32ERd32 ---- 2 Rd16Rs16Rd16 ---- Rd16#xx:16Rd16 ---- 2 Rd8Rs8Rd8 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- Rd8#xx:8Rd8 ---- 0--
Operation
I H N Z V C Normal Advanced 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1
(3) Logical Instructions
AND
AND.B #xx:8,Rd
Appendix A. Instruction Set
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
NOT.L ERd
Rev.4.00 Feb. 13, 2007 Page 622 of 846 REJ09B0354-0400
AND.L ERs,ERd
OR
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
XOR
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
NOT
NOT.B Rd
NOT.W Rd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
(4) Shift Instructions
Mnemonic B B W W L L B B W W MSB L L B B W W L L 2 2 2 2 C MSB LSB 2 0 2 2 2 2 2 LSB C 2 2 2 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 C MSB LSB ---- 2 0 ---- 2 ---- 2 ----
Operation
I H N Z V C Normal Advanced 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SHAL
SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
SHAR
SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
SHLL
SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd

Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 623 of 846 REJ09B0354-0400
SHLL.L #2,ERd
SHLL.L ERd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
--
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa
Mnemonic B B W W L L B B W W C MSB L L B B W W L L 2 2 2 2 2 2 -- -- -- -- MSB -- -- LSB C 2 -- 2 -- 2 -- 2 -- LSB 2 -- 2 -- 2 -- 2 -- 2 -- MSB LSB C 2 -- 0 ---- 0 ---- 0 2 -- ---- 0 2 -- ---- 0 0 0 0 0 0 ---- 0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0 0 0 0 0 0 0 0 0 0 0 0 0
Operation
I H N Z V C Normal Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SHLR
SHLR.B Rd
Appendix A. Instruction Set
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
---- 0

ROTXR.L #2,ERd
Rev.4.00 Feb. 13, 2007 Page 624 of 846 REJ09B0354-0400
SHLR.L #2,ERd
ROTXL
ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
ROTXR
ROTXR.B Rd
ROTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B B W W C MSB LSB L L B B W W MSB -- 1 L L 2 2 2 2 -- LSB C 2 -- 2 -- 2 2 2 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 ---- 2 ---- 0 0 0 0 0 0 0 0 0 0 0 0
Operation
I H N Z V C Normal Advanced 1 1 1 1 1 1 1 1 1 1 1 1
ROTL
ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
ROTR
ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L #2,ERd
ROTR.L ERd
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 625 of 846 REJ09B0354-0400
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B B B B B B B B B B B B B B B B B B B 6 4 4 2 8 6 4 4 2 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 8 (Rn8 of @aa:32)1 6 (Rn8 of @aa:16)1 4 (Rn8 of @aa:8)1 4 (Rn8 of @ERd)1 2 (Rn8 of Rd8)1 8 (#xx:3 of @aa:32)1 6 (#xx:3 of @aa:16)1 4 (#xx:3 of @aa:8)1 4 (#xx:3 of @ERd)1 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 (#xx:3 of Rd8)1 ------------
Operation
I H N Z V C Normal Advanced 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5
BSET
BSET #xx:3,Rd
Appendix A. Instruction Set
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
(5) Bit-Manipulation Instructions
BSET #xx:3,@aa:32
Rev.4.00 Feb. 13, 2007 Page 626 of 846 REJ09B0354-0400
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BCLR
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic Operation (Rn8 of @aa:32)0 B B B [ (#xx:3 of @ERd)] B [ (#xx:3 of @aa:8)] B [ (#xx:3 of @aa:16)] B 8 (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] B B B B 6 4 4 2 (Rn8 of Rd8)[ (Rn8 of Rd8)] 6 (#xx:3 of @aa:16) 4 (#xx:3 of @aa:8) 4 (#xx:3 of @ERd) 2 8
I H N Z V C Normal Advanced ------------ 6 1 4
BCLR
BCLR Rn,@aa:32
BNOT
BNOT #xx:3,Rd
(#xx:3 of Rd8)[ (#xx:3 of Rd8)] -- -- -- -- -- -- ------------
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
------------
4
BNOT #xx:3,@aa:16
------------
5
BNOT #xx:3,@aa:32
------------
6
BNOT Rn,Rd
------------
1 4 4
BNOT Rn,@ERd
(Rn8 of @ERd)[ (Rn8 of @ERd)] -- -- -- -- -- -- (Rn8 of @aa:8)[ (Rn8 of @aa:8)] -- -- -- -- -- -- (Rn8 of @aa:16) [ (Rn8 of @aa:16)] ------------
BNOT Rn,@aa:8
BNOT Rn,@aa:16
5
BNOT Rn,@aa:32
B
8
(Rn8 of @aa:32) [ (Rn8 of @aa:32)]
------------
6
BTST B B B 4
BTST #xx:3,Rd
B
2
(#xx:3 of Rd8)Z (#xx:3 of @ERd)Z 4 6 (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z
------ ------ ------ ------
---- ---- ---- ----
1 3 3 4
BTST #xx:3,@ERd
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 627 of 846 REJ09B0354-0400
BTST #xx:3,@aa:16
BTST #xx:3,@aa:8
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B B B B B B B B B B B B B B B B B B B 4 4 2 8 6 4 4 2 8 6 4 (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) 4 (#xx:3 of @ERd)C 2 (#xx:3 of Rd8)C 8 (Rn8 of @aa:32)Z 6 (Rn8 of @aa:16)Z 4 (Rn8 of @aa:8)Z 4 (Rn8 of @ERd)Z ------ ------ ------ ------ 2 (Rn8 of Rd8)Z ------ 8 (#xx:3 of @aa:32)Z ------
Operation
I H N Z V C Normal Advanced ---- ---- ---- ---- ---- ---- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ------------ ------------ ------------ 1 4 4
BTST
BTST #xx:3,@aa:32
Appendix A. Instruction Set
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BILD #xx:3,@aa:32
BST
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
Rev.4.00 Feb. 13, 2007 Page 628 of 846 REJ09B0354-0400
BTST Rn,@aa:16
BTST Rn,@aa:32
BLD
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BILD
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B B B B B B B B B B B B B B B B B B B 4 2 8 6 4 4 2 8 6 4 4 2 C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C 8 C(#xx:3 of @aa:32) 6 C(#xx:3 of @aa:16) 4 C(#xx:3 of @aa:8) 4 C(#xx:3 of @ERd) 2 C(#xx:3 of Rd8) 8 C(#xx:3 of @aa:32) 6 C(#xx:3 of @aa:16)
Operation
I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3
BST
BST #xx:3,@aa:16
BST #xx:3,@aa:32
BIST
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
BAND
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BIAND
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 629 of 846 REJ09B0354-0400
BOR #xx:3,@ERd
BOR
BOR #xx:3,Rd
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B B B B B B B B B B B B B B B B B B 6 8 4 4 2 8 6 4 4 2 C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C 8 6 C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C 4 C[ (#xx:3 of @aa:8)]C 4 C[ (#xx:3 of @ERd)]C 2 C[ (#xx:3 of Rd8)]C 8 C(#xx:3 of @aa:32)C 6 C(#xx:3 of @aa:16)C 4 C(#xx:3 of @aa:8)C ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
Operation
I H N Z V C Normal Advanced 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5
BOR
BOR #xx:3,@aa:8
Appendix A. Instruction Set
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BIOR
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIXOR #xx:3,@aa:32
Rev.4.00 Feb. 13, 2007 Page 630 of 846 REJ09B0354-0400
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
BXOR
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
BIXOR
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
Addressing Mode/ Instruction Length (Bytes)
Operation Condition Code
Branching Condition
Operand Size
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 V=0 2 4 Z=1 2 4 Z=0 2 4 C=1 2 4 C=0 2 CZ=1 4 2 CZ=0 4 2 else next; Never 4 PCPC+d ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 if condition is true then Always ------------
I H N Z V C Normal Advanced 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3
(6) Branch Instructions
Bcc
BRA d:8(BT d:8)
BRA d:16(BT d:16)
BRN d:8(BF d:8)
BRN d:16(BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:B(BHS d:8)
BCC d:16(BHS d:16)
BCS d:8(BLO d:8)
BCS d:16(BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 631 of 846 REJ09B0354-0400
BVC d:16
Addressing Mode/ Instruction Length (Bytes)
Operation Condition Code
Branching Condition
Operand Size
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 2 4 2 4 NV=1 2 4 NV=0 2 N=1 4 2 N=0 4 2 V=1
I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 3 2 3 2 3 2 3 2 3
Bcc
BVS d:8
Appendix A. Instruction Set
BVS d:16
BPL d:8
BPL d:16
BMI d:8
Rev.4.00 Feb. 13, 2007 Page 632 of 846 REJ09B0354-0400
ZNV)=0 -- -- -- -- -- -- ------------ Z(NV)=1 -- -- -- -- -- -- ------------ 2 3 2 3
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic -- -- -- -- -- -- -- -- -- 2 PC@SP+ 2 PC@-SP,PC@aa:8 4 PC@-SP,PCaa:24 2 PC@-SP,PCERn 4 PC@-SP,PCPC+d:16 2 PC@-SP,PCPC+d:8 2 PC@aa:8 4 PCaa:24 2 PCERn
Operation
I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 4 3 4 3 4 4 4 2 3 5 4 5 4 5 6 5
JMP
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR
BSR d:8
BSR d:16
JSR
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
RTS
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 633 of 846 REJ09B0354-0400
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic -- EXR@-SP,PC EXR@SP+,CCR@SP+, PC@-SP,CCR@-SP, 1 ---------- 7 [9]
Operation
I H N Z V C Normal Advanced 8 [9]
Appendix A. Instruction Set
TRAPA
TRAPA #xx:2

(7) System Control Instructions
PC@SP+ -- Transition to power-down state ------------ 2
SLEEP
SLEEP

LDC Rs,CCR B W W W W W W W W W W W W 6 8 8 6 4 4 10 10 6 6 4 @ERsEXR @(d:16,ERs)CCR @(d:16,ERs)EXR @(d:32,ERs)CCR @(d:32,ERs)EXR 4 @ERsCCR 2 Rs8EXR
B
2
LDC Rs,EXR
------------

LDC @ERs,CCR
LDC @ERs,EXR
------------

LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
------------

LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
------------

LDC @ERs+,CCR
@ERsCCR,ERs32+2ERs32 @ERsEXR,ERs32+2ERs32 @aa:16CCR @aa:16EXR @aa:32CCR @aa:32EXR

Rev.4.00 Feb. 13, 2007 Page 634 of 846 REJ09B0354-0400
B2 B4 Rs8CCR #xx:8EXR ------------
LDC
LDC #xx:8,CCR

#xx:8CCR

RTE
RTE
--
5 [9]
1 2 1 1 3 3 4 4 6 6 4
LDC #xx:8,EXR
LDC @ERs+,EXR
------------
4 4 ------------ 4 5 ------------ 5
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic B B W W W W W W W W W W W W B2 B4 B2 B4 B2 B4 -- 8 8 6 6 4 CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR 2 PCPC+2 4 10 EXR@(d:32,ERd) 10 CCR@(d:32,ERd) 6 EXR@(d:16,ERd) 6 CCR@(d:16,ERd) 4 EXR@ERd 4 CCR@ERd 2 EXRRd8 2 CCRRd8
Operation
I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 1 3 3 4 4 6 6 4 ------------ ------------ ------------ ------------ ------------ 4 4 4 5 5
STC
STC CCR,Rd
STC EXR,Rd
STC CCR,@ERd
STC EXR,@ERd
STC CCR,@(d:16,ERd)
STC EXR,@(d:16,ERd)
STC CCR,@(d:32,ERd)
STC EXR,@(d:32,ERd)
STC CCR,@-ERd
ERd32-2ERd32,CCR@ERd -- -- -- -- -- -- ERd32-2ERd32,EXR@ERd
STC EXR,@-ERd
STC CCR,@aa:16
STC EXR,@aa:16
STC CCR,@aa:32
STC EXR,@aa:32

ANDC
ANDC #xx:8,CCR
1 ------------ 2
ANDC #xx:8,EXR

ORC
ORC #xx:8,CCR
1 ------------ 2
ORC #xx:8,EXR

XORC
XORC #xx:8,CCR
1 ------------ ------------ 2 1
XORC #xx:8,EXR
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 635 of 846 REJ09B0354-0400
NOP
NOP
Addressing Mode/ Instruction Length (Bytes)
Operand Size
Condition Code
No. of States*1
#xx Rn
@ERn
@(d,ERn) @aa
@-ERn/@ERn+ @(d,PC) @@aa --
Mnemonic -- 4 if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; 4 if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; ------------ ------------
Operation
I H N Z V C Normal Advanced 4+2n *2
Appendix A. Instruction Set
(8) Block Transfer Instructions
Rev.4.00 Feb. 13, 2007 Page 636 of 846 REJ09B0354-0400
-- 4+2n *2
EEPMOV
EEPMOV.B
EEPMOV.W
Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2355 Group. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid.
A.2
Instruction 1st byte 8 0 7 0 7 0 0 0 0 9 IMM rs IMM rs 6 rs 6 0 erd 0 0 ers 0 erd IMM 4 IMM 0 IMM 0 erd 0 IMM 0 IMM abs abs 7 6 0 0 IMM 0 7 6 0 IMM 0 abs 1 3 disp 0 disp disp 1 disp 0 0 0 0 7 6 0 7 6 0 rd 1 0 6 6 6 IMM F rd rd IMM rd rd 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 8 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 1 0 erd IMM 9 rs rd 9 1 rd IMM 8 rs rd rd IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- --
Mnemonic
Instruction Format
Size
ADD
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
Table A.2 Instruction Codes
ADDX
ADDX #xx:8,Rd
Instruction Codes
ADDX Rs,Rd
AND
AND.B #xx:8,Rd
Table A.2 shows the instruction codes.
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
Bcc
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 637 of 846 REJ09B0354-0400
BRN d:16 (BF d:16)
Instruction Mnemonic Size 1st byte 4 disp 2 disp 3 disp 4 disp 5 disp 6 disp 7 disp 8 disp 9 disp A disp B disp C disp D disp E disp F 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 8 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16
Instruction Format
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 638 of 846 REJ09B0354-0400
Bcc
Instruction Mnemonic Size 1st byte 7 7 7 6 6 6 7 7 6 6 7 7 7 6 1 IMM 6 7 7 7 6 6 7 7 7 6 6 A 3 0 A 1 0 E abs 7 4 C 0 erd 0 7 4 1 IMM 1 IMM abs abs 4 1 IMM rd 0 0 7 4 1 IMM 0 7 4 1 IMM 0 A 3 0 A 1 0 abs abs 7 E 1 IMM abs 7 7 0 7 1 IMM 0 7 7 1 IMM 0 C 0 erd 1 IMM 0 7 0 7 7 1 IMM rd A abs 3 0 A 1 0 abs 7 6 0 7 6 1 IMM 0 E 1 IMM abs 7 6 0 C 0 erd 1 IMM 0 7 6 0 6 1 IMM rd A abs 3 8 6 2 A 1 abs 8 6 2 rn 0 rn 0 F abs 6 2 rn 0 D 0 erd 0 6 2 rn 0 2 rn rd A abs 0 IMM 0 3 8 7 2 A 0 IMM 1 abs 8 7 2 0 F abs 0 IMM 7 2 0 D 0 erd 0 IMM 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32
Instruction Format 10th byte
BCLR
BIAND
BILD
BIOR
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 639 of 846 REJ09B0354-0400
Instruction Mnemonic Size 1st byte 6 1 IMM 0 erd 0 0 6 abs 6 1 IMM 0 7 7 1 IMM 0 abs 1 abs 3 1 IMM 0 erd 0 0 7 abs 7 5 5 1 IMM 0 1 IMM 0 abs 1 abs 3 0 IMM 0 erd 0 0 7 abs 7 0 IMM 0 7 7 0 IMM 0 abs 1 abs 3 0 IMM 0 erd 0 0 7 abs 1 0 IMM 0 7 1 0 IMM 0 abs 1 abs 1 3 rn 0 erd 1 1 abs abs rn rn abs 1 3 8 8 6 0 6 rd 0 0 6 1 rn 0 6 1 rn 0 8 8 7 0 IMM 0 0 IMM 7 1 rd 0 0 7 0 IMM 7 0 0 IMM 7 7 rd 0 0 7 1 IMM 5 0 1 IMM 7 5 rd 8 8 6 1 IMM 7 0 1 IMM 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32
Instruction Format
BIST
Appendix A. Instruction Set
BIXOR
Rev.4.00 Feb. 13, 2007 Page 640 of 846 REJ09B0354-0400
BLD
BNOT
Instruction Mnemonic Size 1st byte 7 7 7 6 6 abs 0 7 7 7 6 6 abs 6 7 7 6 6 abs 5 disp 0 disp 0 IMM 0 erd 6 0 IMM 0 IMM abs abs 0 6 7 0 IMM 0 6 7 0 IMM 0 6 8 8 rd 0 7 7 0 0 rd 0 6 3 rn 0 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 7 7 0 abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd 0 rd 0 5 6 7 7 6 6 7 7 7 6 6 6 7 C 3 A A E C 3 A A F D 7 C 5 A 3 8 A abs 6 0 rn 1 8 0 6 0 rn 0 F abs 6 0 rn 0 D 0 erd 6 0 rn 0 0 0 rn rd A 3 7 8 0 A abs 0 IMM 7 0 1 0 0 IMM 0 8 F abs 7 0 IMM 0 0 D 0 0 IMM 0 0 erd 0 7 0 0 IMM rd A 0 IMM 3 7 4 0 A abs 0 IMM 7 4 1 0 0 E abs 0 IMM 4 0 7 C 4 0 IMM 0 0 erd 0 7 4 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B -- -- B B B B B B B B B B B B BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd
Instruction Format 10th byte
BOR
BSET
BSR
BST
BTST
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 641 of 846 REJ09B0354-0400
Instruction Mnemonic Size 1st byte 7 6 6 7 7 7 6 6 abs Cannot be used in the H8S/2355 Group A 1 7 IMM 1 7 0 erd IMM 1 0 1 1 1 1 1 0 erd 0 erd 0 0 rd 0 erd C 4 5 5 9 9 8 8 F F 5 3 5 1 rs rs rd 0 erd 1 0 0 5 5 7 7 B D B 5 3 rs 1 rs 1 D 1 D B F B 7 B D rd B 5 rd A 0 rd F 0 rd F 0 rd F 1 ers 0 erd A 2 D rs rd 9 2 rd C rs rd rd IMM A 3 0 7 5 0 IMM A abs 0 IMM 1 0 7 5 0 0 E abs 0 IMM 7 5 0 C 0 IMM 0 erd 0 7 5 0 5 0 IMM rd A abs 0 3 0 6 3 rn A abs 1 0 6 3 rn 0 E abs 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32
Instruction Format
BTST
BXOR
Appendix A. Instruction Set
CLRMAC CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd
Rev.4.00 Feb. 13, 2007 Page 642 of 846 REJ09B0354-0400
EEPMOV.W
CMP
DAA
DAS
DEC
DIVXS
DIVXU
EEPMOV EEPMOV.B
Instruction Mnemonic Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 0 ers 0 ers 0 ers 0 ers 0 ers 8 D 6 6 1 0 1 6 6 4 D B B 0 ers 0 ers 0 ers 0 0 0 0 0 0 8 0 0 0 0 0 disp disp 6 6 B B disp disp 2 2 0 0 disp disp 4 4 4 4 4 4 4 4 0 1 7 0 7 1 6 F 0 6 F 1 6 9 0 6 9 0 rs rs 1 0 7 0 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 0 ern B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR
Instruction Format 10th byte
EXTS
EXTU
INC
JMP
JSR
LDC
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 643 of 846 REJ09B0354-0400
Instruction Mnemonic Size 1st byte 0 0 0 0 0 Cannot be used in the H8S/2355 Group 1 7 0 ern+3 3 0 6 D 1 7 0 ern+2 2 0 6 D 1 7 0 ern+1 1 0 6 D 1 2 0 abs 4 1 6 B 1 2 0 abs 4 0 6 B 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W L L L L L -- B B B B B rd B B B B B B B rs B B B B W W W W W 7 8 0 ers 6 F 0 ers rd 0 6 B 6 9 0 ers rd disp 2 rd disp 0 D rs rd 7 9 0 rd 6 A A rs IMM 6 A 8 rs abs abs 3 rs abs 6 C 1 erd rs 7 8 0 erd A 0 6 A 6 E 1 erd disp disp rs 6 8 1 erd rs 6 A abs 2 rd 6 A abs 0 rd 2 rd abs 6 C 0 ers rd 7 8 0 ers 2 0 6 A disp 6 E 0 ers disp rd 6 8 0 ers rd 0 C rs rd F rd IMM LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd
Instruction Format
LDC
LDM
LDMAC
MAC
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 644 of 846 REJ09B0354-0400
MOV
Instruction Mnemonic Size 1st byte 6 6 abs abs 6 6 6 disp 6 disp B A rs 7 6 6 abs abs IMM 6 7 0 erd 0 0 0 ers 0 erd 0 ers 0 erd disp 6 2 B 0 erd disp 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp abs abs 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 6 B 1 0 0 6 B 8 A 1 0 0 6 D 1 0 0 7 8 1 0 0 6 F 1 0 0 6 9 1 0 0 6 B 1 0 0 6 B 1 0 0 6 D 1 0 0 7 8 1 0 0 6 F 1 0 0 6 9 F 1 ers 0 erd A 0 B A rs B 8 rs D 1 erd rs 8 0 erd 0 F 1 erd rs 9 1 erd rs B 2 rd B 0 rd D 0 ers rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)* L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 B B B W B W 5 2 rs 5 0 rs 0 1 C 0 rd 0 erd 0 1 C 0 5 5 0 2 rs rs rd 0 erd L L L
Instruction Format 10th byte
MOV
1 erd 0 ers 0 ers 0 ers abs abs
MOVFPE MOVFPE @aa:16,Rd
Cannot be used in the H8S/2355 Group
MOVTPE MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd
MULXS
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 645 of 846 REJ09B0354-0400
MULXU
Instruction Mnemonic Size 1st byte 1 1 1 0 1 1 1 C 1 7 IMM 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 0 erd F 2 0 erd B 2 rd D 2 rd 9 2 rd C 2 rd 8 1 0 6 D 0 F 0 ern D rn F 1 0 6 D 0 7 0 ern D rn 7 1 1 0 4 4 IMM 4 IMM 1 0 6 4 F 0 ers 0 erd A 0 erd 4 IMM 4 rd rs 9 rd 4 4 rd rs rd IMM 7 3 0 erd 7 rd 1 7 rd 0 0 0 0 7 B 0 erd 7 rd 9 7 rd 8 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B W L -- B W L B B W W L L B B W L W L B B W W L L NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd
Instruction Format
NEG
NOP
NOT
Appendix A. Instruction Set
OR
Rev.4.00 Feb. 13, 2007 Page 646 of 846 REJ09B0354-0400
ORC
POP
PUSH
ROTL
Instruction Mnemonic Size 1st byte 1 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 3 1 3 4 3 0 2 7 2 3 2 5 2 1 2 4 2 0 3 F 3 B 3 D 3 9 3 C 3 8 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L -- -- B B W W L L ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTS SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd
Instruction Format 10th byte
ROTR
ROTXL
ROTXR
RTE
RTS
SHAL
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 647 of 846 REJ09B0354-0400
Instruction Mnemonic Size 1st byte 1 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 7 7 6 6 6 F 8 8 D D 6 F 6 9 6 9 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 2 1 2 0 1 8 1 7 1 3 1 5 1 1 1 4 1 0 0 7 0 3 0 5 0 1 0 4 0 0 1 F 1 B 1 D 1 9 1 C 1 8 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L B B W W L L B B W W L L -- B B W W SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd STC.W EXR,@-ERd W W
Instruction Format
SHAR
Appendix A. Instruction Set
SHLL
Rev.4.00 Feb. 13, 2007 Page 648 of 846 REJ09B0354-0400
SHLR
SLEEP
STC
Instruction Mnemonic Size 1st byte 0 0 0 0 0 0 0 Cannot be used in the H8S/2355 Group 1 0 ern 3 0 6 D F 1 0 ern 2 0 6 D F 1 0 ern 1 0 6 D F 1 0 abs 4 1 6 B A 1 0 abs 4 0 6 B A 1 0 abs 4 1 6 B 8 1 0 abs 4 0 6 B 8 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B 1 7 IMM 1 7 IMM 1 1 1 1 B IMM rs E 0 erd C 00 IMM IMM rs 5 rs 5 F 0 0 erd 6 5 rd IMM 0 ers 0 erd rd rd IMM 0 0 7 B rd 1 0 5 D 1 7 6 7 0 1 A 5 9 5 rd 7 1 E rd B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 3 0 erd 9 rs rd 9 3 rd W W L L L L L B B B -- B B W W L L 8 rs rd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd
Instruction Format 10th byte
STC
STM
STMAC
SUB
SUBS
SUBX
TAS
TRAPA
XOR
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 649 of 846 REJ09B0354-0400
Instruction Mnemonic Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B XORC #xx:8,CCR XORC #xx:8,EXR
Instruction Format
XORC
Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm:
Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.)
Appendix A. Instruction Set
Note: * Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0.
The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 * * * 0111 1000 1001 * * * 1111 R0 R1 * * * R7 E0 E1 * * * E7 0000 0001 * * * 0111 1000 1001 * * * 1111 R0H R1H * * * R7H R0L R1L * * * R7L General Register Register Field General Register 8-Bit Register
Address Register 32-Bit Register General Register ER0 ER1 * * * ER7
Rev.4.00 Feb. 13, 2007 Page 650 of 846 REJ09B0354-0400
Register Field
000 001 * * * 111
Instruction when most significant bit of BH is 0. 2nd byte BH BL Instruction when most significant bit of BH is 1.
A.3
Instruction code
1st byte
AH
AL
AL 3 4 ORC OR MOV.B XOR AND SUBX Table A.3(2) SUB CMP XORC ANDC LDC ADDX ADD MOV 5 6 7 9 B D E C A 8 F
AH
0
1
2
0
NOP
1
Table A.3(2)
LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2)
2
3 BLS BCC BVS BLT JSR MOV Table A.3(3) JMP BSR BPL BMI BGE RTS OR MOV Table A.3(2) XOR MOV AND BST Table A.3(2) Table A.3(2) EEPMOV BSR RTE TRAPA Table A.3(2) BCS BNE BEQ BVC BGT DIVXU BTST BLE
4
BRA
BRN
BHI
5
MULXU
DIVXU
MULXU
6 BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND ADD ADDX CMP SUBX OR XOR AND MOV
Operation Code Map
BSET
BNOT
BCLR
Table A.3 Operation Code Map (1)
Table A.3 shows the operation code map.
7
8
9
A
B
C
D
E
F
Note: * Cannot be used in the H8S/2355 Group.
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 651 of 846 REJ09B0354-0400
Instruction code AH AL BH BL
1st byte
2nd byte
BH 1 5 6 C Table A.3(3) TAS ADD INC MOV SHLL SHLL SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUBS CMP BRN BCS BNE MOV XOR AND AND XOR BEQ BVC Table A.3(4) MOV CMP OR OR CMP SUB SUB ADD ADD Table * A.3(4) MOVFPE BHI BLS BCC BVS BPL MOV BMI BGE MOVTPE* BLT BGT DEC EXTS SHLR ROTXL ROTXR EXTU EXTU NEG ROTR ROTL SHAR SHAL SHLR ROTXL ROTXR NOT NOT ROTXR ROTXL SHLR SHLL INC INC ADDS Table A.3(3) MAC* SLEEP CLRMAC * B 7 D E 8 9 A LDM STM STC LDC 2 3 4 F
AH AL
0
01
MOV
Table A.3(3)
0A
INC
0B
ADDS
INC
0F
DAA
Appendix A. Instruction Set
10
SHAL SHAR ROTL ROTR EXTS
11
12
Table A.3 Operation Code Map (2)
13
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DEC BLE
17
1A
DEC
1B
SUBS
1F
DAS
58
BRA
6A
MOV
79
MOV
7A
MOV
Note: * Cannot be used in the H8S/2355 Group.
Instruction code AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1.
1st byte
2nd byte
3rd byte 4th byte
CL 0 MULXS DIVXS OR BTST BTST BSET BSET BTST BTST BSET BSET BNOT BCLR BNOT BCLR BNOT BCLR BNOT BCLR XOR AND DIVXS MULXS 1 2 3 4 5 6 7 8 9 A B C D E
AH AL BH BL CH
F
01C05
01D05
01F06
7Cr06 *1
7Cr07 *1
7Dr06
*1
BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST
7Dr07 *1
Table A.3 Operation Code Map (3)
7Eaa6 *2
7Eaa7
*2
7Faa6
*2
BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST
7Faa7 *2
Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
Appendix A. Instruction Set
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Instruction code AH Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 0 1 4 5 6 7 8 9 A B C D E BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 2 3 F AL BH BL CH CL DH EH EL FH DL FL
1st byte
2nd byte
3rd byte 4th byte 6th byte
5th byte
EL
AHALBHBLCHCLDHDLEH
6A10aaaa6*
6A10aaaa7*
6A18aaaa6* BSET BNOT BCLR
Appendix A. Instruction Set
6A18aaaa7*
Table A.3 Operation Code Map (4)
Instruction code AH AL BH BL CH CL DH EH EL FH FL DL GH
1st byte
2nd byte
3rd byte 4th byte 6th byte
5th byte
7th byte GL
8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1.
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0 4 5 6 7 8 BTST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 1 2 3 9 A B C D E F BSET BNOT BCLR
GL
AHALBHBL ... FHFLGH
6A30aaaaaaaa6*
6A30aaaaaaaa7*
6A38aaaaaaaa6*
6A38aaaaaaaa7*
Note: * aa is the absolute address specification.
Appendix A. Instruction Set
A.4
Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: SI = 4, SL = 2 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: SI = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24
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Appendix A. Instruction Set
Table A.4
Number of States per Cycle
Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus 2 16-Bit Bus
Cycle Instruction fetch SI SK SL SM SN
On-Chip 8-Bit Memory Bus 1 4
2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m
Branch address read SJ Stack operation Byte data access Word data access Internal operation 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1
Legend: m: Number of wait states inserted into external device access
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Appendix A. Instruction Set
Table A.5
Number of Cycles in Instruction Execution
Instruction Fetch Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N
Instruction ADD
Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd
I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 (BHS d:8) (BLO d:8) 2 2 2 2 2 2 2 2 2 2 2 2 (BT d:16) (BF d:16) 2 2
ADDS ADDX
ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd
AND
AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd
ANDC
ANDC #xx:8,CCR ANDC #xx:8,EXR
BAND
BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32
1 1 1 1
Bcc
BRA d:8 BRN d:8 BHI d:8 BLS d:8 BCC d:8 BCS d:8 BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 BRN d:16
(BT d:8) (BF d:8)
1 1
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction Bcc Mnemonic BHI d:16 BLS d:16 BCC d:16 BCS d:16 BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 (BHS d:16) (BLO d:16) I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4
Stack Operation K
Byte Data Access L
Word Data Access M
Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2
2 2 2 2
1 1 1 1
1 1 1 1
1 1 1 1
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction BIST Mnemonic BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4
Stack Operation K
Byte Data Access L 2 2 2 2
Word Data Access M
Internal Operation N
1 1 1 1
1 1 1 1
2 2 2 2
2 2 2 2
1 1 1 1
2 2 2 2
2 2 2 2
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction BSR Mnemonic BSR d:8 Normal Advanced BSR d:16 Normal Advanced BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4
Stack Operation K 1 2 1 2
Byte Data Access L
Word Data Access M
Internal Operation N
1 1
2 2 2 2
1 1 1 1
1 1 1 1
1 1 1 1
Cannot be used in the H8S/2355 Group 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 11 19 11 19
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Advanced JSR JSR @ERn Normal Advanced JSR @aa:24 Normal Advanced JSR @@aa:8 Normal Advanced LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2
Stack Operation K
Byte Data Access L 2n+2 *2 2n+2 *2
Word Data Access M
Internal Operation N
1 1 2 1 2 1 2 1 2 1 2 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1
Cannot be used in the H8S/2355 Group
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction MAC MOV Mnemonic MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) I 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3
Stack Operation K
Byte Data Access L
Word Data Access M
Internal Operation N
Cannot be used in the H8S/2355 Group
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 1
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction MOV Mnemonic MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 I 5 2 3 4
Stack Operation K
Byte Data Access L
Word Data Access M 2 2 2 2
Internal Operation N 1
Can not be used in the H8S/2355 Group
11 19 11 19
1 2 1 2
1 1 1 1
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction ROTXL Mnemonic ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS RTE RTS Normal Advanced SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP I 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Stack Operation K
Byte Data Access L
Word Data Access M
Internal Operation N
2 / 3 *1 1 2
1 1 1
1
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Appendix A. Instruction Set
Branch Address Read J
Instruction Fetch Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA TAS @ERd Normal Advanced XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR 1 2 1 3 1 1 1 1 2 2 2 1 1 2 1 3 2 1 2 I 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2
Stack Operation K
Byte Data Access L
Word Data Access M
Internal Operation N
1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1
Cannot be used in the H8S/2355 Group
2 1 2 2 / 3 *1 2 / 3 *1 2 2
TRAPA #x:2
Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred.
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Appendix A. Instruction Set
A.5
Bus States During Instruction Execution
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table:
Order of execution Instruction
JMP@aa:24
1
R:W 2nd
2
3
4
5
6
7
8
Internal operation R:W EA 1 state
End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read)
Legend: R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address
Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states.
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Appendix A. Instruction Set
Address bus RD HWR, LWR
High level
R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction
Internal operation
R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address
Figure A.1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States)
Rev.4.00 Feb. 13, 2007 Page 667 of 846 REJ09B0354-0400
2
3
4
5
6
7
8
9
R:W NEXT R:W 3rd R:W NEXT
Appendix A. Instruction Set
R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT
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Table A.6 Instruction Execution Cycles
Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8
1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT
3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA
Instruction BLE d:8 BRA d:16 (BT d:16) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:B:M EA R:B:M EA R:W 3rd
1 R:W NEXT R:W 2nd
4
5
6
7
8
9
BRN d:16 (BF d:16)
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
Appendix A. Instruction Set
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BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16
2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
Appendix A. Instruction Set
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3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT
Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd
2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W stack W:W:M stack (H) R:W EA W:W stack (L) W:W stack W:W:M stack (H) W:W stack (L) R:W EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 Normal BSR d:8 Advanced Normal BSR d:16 R:W 2nd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA R:W EA Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd
3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th
4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
7
8
9
Advanced
Appendix A. Instruction Set
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R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd
BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd
W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA
Appendix A. Instruction Set
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1 2 3 4 5 6 R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W: NEXT R:W 2nd R:W 3rd R:W 4th R:B EA R:W: NEXT R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT Cannot be used in the H8S/2355 Group R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT Internal operation, 11 states R:W 2nd R:W NEXT Internal operation, 19 states R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:W NEXT R:W 2nd R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:W NEXT R:W 2nd R:B EAs*1 R:W NEXT Repeated n times*2 R:W NEXT R:W NEXT R:W NEXT R:W NEXT 7 8 9
Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd
Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W NEXT
1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd
2
3
4
5
6
7
8
9
JMP @@aa:8 Normal
Advanced R:W NEXT
JSR @ERn
JSR @aa:24
Normal R:W NEXT Advanced R:W NEXT Normal R:W 2nd
Advanced R:W 2nd
R:W EA Internal operation, R:W EA 1 state R:W aa:8 Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W stack R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W stack 1 state Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W aa:8 W:W stack R:W EA R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA R:W NEXT
JSR @@aa:8 Normal Advanced LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W NEXT R:W NEXT R:W EA R:W EA R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd
R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd
LDC @ERs+,EXR
Appendix A. Instruction Set
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LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1)
R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state
Instruction LDM.L @SP+,(ERn-ERn+2)
1 R:W 2nd
2 R:W NEXT
6
7
8
9
Appendix A. Instruction Set
LDM.L @SP+,(ERn-ERn+3)
3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W 2nd R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Cannot be used in the H8S/2355 Group
LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W 4th R:B EA R:W NEXT R:B EA
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R:B EA R:W NEXT R:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W EA R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA
MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd
MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd
MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd
4 R:W NEXT W:W EA
Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd
1 R:W 2nd R:W 2nd R:W NEXT
3 W:W EA R:E 4th W:W EA
5
6
7
8
9
2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA
MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W 5th R:W:M EA
R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd
MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd W:W EA+2 R:W NEXT W:W EA+2 W:W EA+2 W:W:M EA W:W:M EA W:W:M EA R:W NEXT
R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA
W:W EA+2
R:W: EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W: EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the H8S/2355 Group W:W EA+2 R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states
MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 675 of 846 REJ09B0354-0400
2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT
Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT W:W EA+2 R:W EA+2
1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT
3
4
5
6
7
8
9
POP.L ERn
Appendix A. Instruction Set
PUSH.W Rn
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R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state
PUSH.L ERn
ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd
2 R:W stack (EXR) R:W stack (H) R:W stack R:W stack (L) Internal operation, R:W*4 1 state
Instruction ROTXR.L #2,ERd RTE R:W NEXT
1 R:W NEXT R:W NEXT
3
4
5
6
7
8
9
RTS
Normal
Advanced R:W NEXT
Internal operation, R:W*4 1 state R:W:M stack (H) R:W stack (L) Internal operation, R:W*4 1 state
SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA
R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 677 of 846 REJ09B0354-0400
5 R:W NEXT R:W NEXT W:W EA W:W EA
Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd W:W EA W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd
2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT
4 W:W EA R:W 5th R:W 5th W:W EA
6
7
8
9
Appendix A. Instruction Set
STC EXR,@-ERd
STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn-ERn+1),@-SP
STM.L(ERn-ERn+2),@-SP
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3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state Cannot be used in the H8S/2355 Group R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT W:B EA W:W stack (H) W:W stack (H) R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state Internal operation, W:W stack (L) 1 state W:W stack (EXR) R:W VEC W:W stack (EXR) R:W:M VEC Internal operation, R:W*7 1 state R:W VEC+2 Internal operation, R:W*7 1 state R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT
STM.L(ERn-ERn+3),@-SP
STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 Normal
Advanced R:W NEXT
XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd
Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Normal Reset exception handling Advanced R:W VEC W:W stack (EXR) W:W stack (EXR) R:W:M VEC R:W VEC R:W NEXT Internal operation, R:W*5 1 state R:W VEC+2 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state Internal operation, R:W*7 1 state R:W VEC+2 Internal operation, R:W*7 1 state
1 R:W 2nd R:W NEXT R:W 2nd R:W VEC
2 R:W NEXT
3
4
5
6
7
8
9
R:W*6 Interrupt exception Normal handling Advanced R:W*6
Notes: 1. 2.
3. 4. 5. 6.
7.
EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. Start address after return. Start address of the program. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. Start address of the interrupt-handling routine.
Appendix A. Instruction Set
Rev.4.00 Feb. 13, 2007 Page 679 of 846 REJ09B0354-0400
Appendix A. Instruction Set
A.6
Condition Code Modification
This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn -- The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution
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Appendix A. Instruction Set
Table A.7
Instruction ADD
Condition Code Modification
H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm
ADDS ADDX
---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm
AND ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC
--
0
--
N = Rm Z = Rm * Rm-1 * ...... * R0 Stores the corresponding bits of the result. No flags change when the operand is EXR.
-------- ---------- ---------- -------- -------- -------- ---------- -------- -------- ---------- -------- ---------- ---------- ---------- ---- ----
C = C' * Dn
C = C' * Dn C = Dn C = C' + Dn C = C' * Dn + C' * Dn C = Dn
C = C' + Dn
Z = Dn C = C' * Dn + C' * Dn Cannot be used in the H8S/2355 Group Rev.4.00 Feb. 13, 2007 Page 681 of 846 REJ09B0354-0400
--------
Appendix A. Instruction Set Instruction CMP H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm DAA * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic borrow DEC -- -- N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm DIVXS DIVXU EEPMOV EXTS EXTU INC -- -- ---- ---- N = Sm * Dm + Sm * Dm Z = Sm * Sm-1 * ...... * S0 N = Sm Z = Sm * Sm-1 * ...... * S0 ---------- -- --0 -- 0 0 -- -- -- N = Rm Z = Rm * Rm-1 * ...... * R0 Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm JMP JSR LDC LDM LDMAC MAC ---------- Cannnot be used in the H8S/2355 Group ---------- ---------- Stores the corresponding bits of the result. No flags change when the operand is EXR.
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Appendix A. Instruction Set Instruction MOV MOVFPE MOVTPE MULXS MULXU NEG -- ---- N = R2m Z = R2m * R2m-1 * ...... * R0 ---------- H = Dm-4 + Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm C = Dm + Rm NOP NOT OR ORC POP PUSH ROTL -- -- -- 0 0 0 -- -- ---------- -- -- 0 0 -- -- N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) H -- N Z V 0 C -- Definition N = Rm Z = Rm * Rm-1 * ...... * R0 Can not be used in the H8S/2355 Group
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Appendix A. Instruction Set Instruction ROTXL H -- N Z V 0 C Definition N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTXR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ---------- -- N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Dm-1 + Dm * Dm-1 (1-bit shift) V = Dm * Dm-1 * Dm-2 * Dm * Dm-1 * Dm-2 (2-bit shift) C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHAR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHLR --0 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ---------- ---------- ---------- Cannot be used in the H8S/2355 Group Stores the corresponding bits of the result.
Rev.4.00 Feb. 13, 2007 Page 684 of 846 REJ09B0354-0400
Appendix A. Instruction Set Instruction SUB H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm SUBS SUBX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm TAS TRAPA XOR XORC -- 0 -- N = Dm Z = Dm * Dm-1 * ...... * D0 ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 Stores the corresponding bits of the result. No flags change when the operand is EXR.
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Appendix B. Internal I/O Register
Appendix B Internal I/O Register
B.1 Addresses
Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz Module Name DTC Data Bus Width 16/32*1 bit
Address Register (low) Name Bit 7 H'F800 to H'FBFF MRA SAR SM1
MRB DAR
CHNE
DISEL
--
--
--
--
--
--
CRA
CRB
H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F
TCR3 TMDR3
CCLR2 --
CCLR1 -- IOB2 IOD2 -- --
CCLR0 BFB IOB1 IOD1 -- --
CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC
TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TPU3
16 bit
TIOR3H IOB3 TIOR3L TIER3 TSR3 TCNT3 IOD3 TTGE --
TGR3A
TGR3B
TGR3C
TGR3D
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Appendix B. Internal I/O Register
Address Register (low) Name Bit 7 H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEB2 H'FEB4 H'FEB5 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF P1DDR P2DDR P3DDR P5DDR P6DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR -- -- -- -- P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR -- -- P53DDR P52DDR P51DDR P50DDR
Bit 6 CCLR1 -- IOB2 -- --
Bit 5 CCLR0 -- IOB1 TCIEU TCFU
Bit 4
Bit 3
Bit 2
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA
Module Name TPU4
Data Bus Width 16 bit
TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4
-- -- IOB3 TTGE TCFD
CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- --
TGR4A
TGR4B
TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5
-- -- IOB3 TTGE TCFD
CCLR1 -- IOB2 -- --
CCLR0 -- IOB1 TCIEU TCFU
CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU5
16 bit
TGR5A
TGR5B
Port
8 bit
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR -- -- PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
PGDDR --
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Appendix B. Internal I/O Register
Address Register (low) Name Bit 7 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FF2C H'FF2D H'FF2E H'FF2F IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK -- -- -- -- -- -- -- -- -- -- -- Data Bus Width 8 bit
Bit 6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 --
Bit 5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21
Bit 4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20
Bit 3 -- -- -- -- -- -- -- -- -- -- -- ABW3 AST3 W51 W11
Bit 2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10
Bit 1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 -- --
Bit 0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 -- WAITE
Module Name Interrupt controller
ABWCR ABW7 ASTCR WCRH WCRL BCRH BCRL ISCRH ISCRL IER ISR AST7 W71 W31 ICIS1 BRLE
Bus controller
8 bit
BRSTRM BRSTS1 BRSTS0 --
EAE
--
--
--
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Interrupt controller
8 bit
IRQ7E IRQ7F DTCE7
IRQ6E IRQ6F DTCE6
IRQ5E IRQ5F DTCE5
IRQ4E IRQ4F DTCE4
IRQ3E IRQ3F DTCE3
IRQ2E IRQ2F DTCE2
IRQ1E IRQ1F DTCE1
IRQ0E IRQ0F DTCE0 DTC 8 bit
H'FF30 to DTCER H'FF35 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF3C H'FF3D H'FF44
DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 SBYCR SYSCR SCKCR MDCR SSBY -- STS2 -- STS1 INTM1 -- -- STS0 INTM0 -- -- OPE NMIEG -- -- -- -- SCK2 MDS2 -- -- SCK1 MDS1 -- RAME SCK0 MDS0 MSTP8 Power-down mode MCU Clock pulse generator MCU Power-down mode Reserved -- 8 bit 8 bit 8 bit 8 bit 8 bit
PSTOP -- -- --
MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7
MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 -- -- -- -- -- -- --
Reserved --
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Appendix B. Internal I/O Register
Address Register (low) Name Bit 7 H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF55 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF64 H'FF65 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR P17 P27 -- P47 -- P67 PA7 PB7 PC7 PD7 PE7 PF7 -- P17DR P27DR -- -- P67DR Data Bus Width 8 bit
Bit 6 P16 P26 -- P46 -- P66 PA6 PB6 PC6 PD6 PE6 PF6 -- P16DR P26DR -- -- P66DR
Bit 5 P15 P25 P35 P45 -- P65 PA5 PB5 PC5 PD5 PE5 PF5 -- P15DR P25DR P35DR -- P65DR
Bit 4 P14 P24 P34 P44 -- P64 PA4 PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR -- P64DR
Bit 3 P13 P23 P33 P43 P53 P63 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR
Bit 2 P12 P22 P32 P42 P52 P62 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR
Bit 1 P11 P21 P31 P41 P51 P61 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR
Bit 0 P10 P20 P30 P40 P50 P60 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR
Module Name Port
PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR PF7DR -- PF6DR -- PF5DR -- PF4DR PF3DR PF2DR PF1DR PF0DR
PG4DR PG3DR PG2DR PG1DR PG0DR
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
--
--
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
Rev.4.00 Feb. 13, 2007 Page 689 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
Address Register (low) Name Bit 7 H'FF78 SMR0 C/A/ GM* H'FF79 H'FF7A H'FF7B H'FF7C BRR0 SCR0 TDR0 SSR0 TDRE RDRF ORER FER/ ERS*3 H'FF7D H'FF7E H'FF80 RDR0 SCMR0 SMR1 -- C/A/ GM*2 H'FF81 H'FF82 H'FF83 H'FF84 BRR1 SCR1 TDR1 SSR1 TDRE RDRF ORER FER/ ERS*3 H'FF85 H'FF86 H'FF88 RDR1 SCMR1 SMR2 -- C/A/ GM*2 H'FF89 H'FF8A H'FF8B H'FF8C BRR2 SCR2 TDR2 SSR2 TDRE RDRF ORER FER/ ERS*3 H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H"FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 RDR2 SCMR2 -- -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- SDIR AD5 -- AD5 -- AD5 -- AD5 -- CKS -- SINV AD4 -- AD4 -- AD4 -- AD4 -- -- -- -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- SMIF AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- A/D converter 8 bit PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- CHR -- PE -- O/E SDIR STOP SINV MP -- CKS1 SMIF CKS0 SCI2, Smart card interface 2 8 bit PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- CHR -- PE -- O/E SDIR STOP SINV MP -- CKS1 SMIF CKS0 SCI1, Smart card interface 1 8 bit PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0
2
Bit 6 CHR
Bit 5 PE
Bit 4 O/E
Bit 3 STOP
Bit 2 MP
Bit 1 CKS1
Bit 0 CKS0
Module Name SCI0, Smart card interface 0
Data Bus Width 8 bit
ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR ADF
TRGS1 TRGS0 --
Rev.4.00 Feb. 13, 2007 Page 690 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
Address Register (low) Name Bit 7 H'FFA4 H'FFA5 H'FFA6 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBC (read) H'FFBD (read) H'FFBF (read) H'FFC0 H'FFC1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF TGR0D TGR0C TGR0B TGR0A TSTR TSYR TCR0 TMDR0 -- -- CCLR2 -- -- -- CCLR1 -- IOB2 IOD2 -- -- CST5 CST4 CST3 CST2 CST1 CST0 TPU 16 bit RSTCSR WOVF RSTE RSTS -- -- -- -- -- TCNT DADR0*4 DADR1* DACR* TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 TCSR OVF WT/IT TME -- -- CKS2 CKS1 CKS0 WDT 16 bit
4 4
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
Data Bus Width
D/A converter*4 8 bit
DAOE1 DAOE0 DAE CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF
-- CCLR1 CCLR1 ADTE --
-- CCLR0 CCLR0 OS3 OS3
-- CKS2 CKS2 OS2 OS2
-- CKS1 CKS1 OS1 OS1
-- CKS0 CKS0 OS0 OS0 8-bit timer channel 0, 1 16 bit
SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 CCLR0 BFB IOB1 IOD1 -- -- CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 16 bit
TIOR0H IOB3 TIOR0L TIER0 TSR0 TCNT0 IOD3 TTGE --
Rev.4.00 Feb. 13, 2007 Page 691 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
Address Register (low) Name Bit 7 H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 -- -- IOB3 TTGE TCFD TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 -- -- IOB3 TTGE TCFD
Bit 6 CCLR1 -- IOB2 -- --
Bit 5 CCLR0 -- IOB1 TCIEU TCFU
Bit 4
Bit 3
Bit 2
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA
Module Name TPU1
Data Bus Width 16 bit
CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- --
CCLR1 -- IOB2 -- --
CCLR0 -- IOB1 TCIEU TCFU
CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU2
16 bit
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. Functions as C/A for SCI use, and as GM for smart card interface use. 3. Functions as FER for SCI use, and as ERS for smart card interface use. 4. In the H8S/2393 these bits are reserved, as a D/A converter is not supported.
Rev.4.00 Feb. 13, 2007 Page 692 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
B.2
Functions
H'F800--H'FBFF
5 DM1 -- 4 DM0 -- 3 MD1 -- 2 MD0 -- 1 DTS -- 0 Sz --
MRA--DTC Mode Register A
Bit : 7 SM1 Initial value : Read/Write : -- 6 SM0 --
DTC
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer
DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 -- 0 1 Source Address Mode 0 1 -- 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode -- Destination side is repeat area or block area Source side is repeat area or block area
Rev.4.00 Feb. 13, 2007 Page 693 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
MRB--DTC Mode Register B
Bit : 7 CHNE Initial value : Read/Write : -- 6 DISEL -- 5 -- -- 4 -- --
H'F800--H'FBFF
3 -- -- 2 -- -- 1 -- -- 0 -- --
DTC
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Reserved Only 0 should be written to these bits DTC Interrupt Select 0 1 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled
DTC Chain Transfer Enable 0 1 End of DTC data transfer DTC chain transfer
SAR--DTC Source Address Register
Bit : 23 22 21 20 19
H'F800--H'FBFF
--------4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
Specifies transfer data source address
DAR--DTC Destination Address Register
Bit : 23 22 21 20 19
H'F800--H'FBFF
--------4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
Specifies transfer data destination address
Rev.4.00 Feb. 13, 2007 Page 694 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
CRA--DTC Transfer Count Register A
Bit : 15 14 13 12 11 10 9 8
H'F800--H'FBFF
7 6 5 4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CRAH
CRAL
Specifies the number of DTC data transfers
CRB--DTC Transfer Count Register B
Bit : 15 14 13 12 11 10 9 8
H'F800--H'FBFF
7 6 5 4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Specifies the number of DTC block data transfers
Rev.4.00 Feb. 13, 2007 Page 695 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR3--Timer Control Register 3
Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FE80
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 R/W
TPU3
Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1
Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 -- Count at rising edge Count at falling edge Count at both edges
Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096
1
0
0 1
1
0 1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Rev.4.00 Feb. 13, 2007 Page 696 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TMDR3--Timer Mode Register 3
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W
H'FE81
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU3
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend: * : Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation
Buffer Operation B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation
Rev.4.00 Feb. 13, 2007 Page 697 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR3H--Timer I/O Control Register 3H
Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W Initial value :
H'FE82
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU3
TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock TGR3A Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is input capture register Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down*1 TGR3B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care
Note: 1. If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and /1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur.
Rev.4.00 Feb. 13, 2007 Page 698 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR3L--Timer I/O Control Register 3L
Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W
H'FE83
2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W
TPU3
TRG3C I/O Control 0
0 0 0 TGR3C Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock
0 output at compare match 1 output at compare match Toggle output at compare match
1
1
0
0
1 1 *
0 TGR3C is input 1 capture * register *
Legend: * : Don't care Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
TGR3D I/O Control 0 0 0
1
0 TGR3D Output disabled is output 1 compare Initial output is 0 0 output at compare match 2 output 0 register* 1 output at compare match 1 Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1
1
0
0 1
1
0 1
1
0
0
1 1 *
0 TGR3D Capture input source is is input 1 capture TIOCD3 pin 2 * register* * Capture input source is channel 4/count clock
Legend: * : Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev.4.00 Feb. 13, 2007 Page 699 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIER3--Timer Interrupt Enable Register 3
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3
H'FE84
2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGIED 0 R/W
TPU3
TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev.4.00 Feb. 13, 2007 Page 700 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSR3--Timer Status Register 3
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)*
H'FE85
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU3
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT=TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
1
Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 701 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT3--Timer Counter 3
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FE86
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU3
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
TGR3A--Timer General Register 3A TGR3B--Timer General Register 3B TGR3C--Timer General Register 3C TGR3D--Timer General Register 3D
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FE88 H'FE8A H'FE8C H'FE8E
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU3 TPU3 TPU3 TPU3
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.4.00 Feb. 13, 2007 Page 702 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR4--Timer Control Register 4
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W
H'FE90
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0
TPU4
Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Counter Clear 0 0 1 1 0 1
Note: This setting is ignored when channel 4 is in phase counting mode.
TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1.
Rev.4.00 Feb. 13, 2007 Page 703 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TMDR4--Timer Mode Register 4
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FE91
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU4
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend: * : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev.4.00 Feb. 13, 2007 Page 704 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR4--Timer I/O Control Register 4
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FE92
1 IOA1 0 R/W 0 IOA0 0 R/W IOA2 0 R/W
TPU4
TGR4A I/O Control 0 0 0 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture
0 output at compare match 1 output at compare match Toggle output at compare match
1
Legend: * : Don't care
TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture
0 output at compare match 1 output at compare match Toggle output at compare match
1
Legend: * : Don't care
Rev.4.00 Feb. 13, 2007 Page 705 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIER4--Timer Interrupt Enable Register 4
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FE94
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU4
Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev.4.00 Feb. 13, 2007 Page 706 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSR4--Timer Status Register 4
Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FE95
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU4
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 707 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT4--Timer Counter 4
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FE96
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU4
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR4A--Timer General Register 4A TGR4B--Timer General Register 4B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FE98 H'FE9A
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU4 TPU4
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.4.00 Feb. 13, 2007 Page 708 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR5--Timer Control Register 5
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W CKEG1 CKEG0
H'FEA0
2 TPSC2 0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64
TPU5
1 TPSC1 0 R/W 0 TPSC0 0 R/W
External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 5 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1.
Rev.4.00 Feb. 13, 2007 Page 709 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TMDR5--Timer Mode Register 5
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FEA1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU5
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend: * : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev.4.00 Feb. 13, 2007 Page 710 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR5--Timer I/O Control Register 5
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FEA2
1 IOA1 0 R/W 0 IOA0 0 R/W IOA2 0 R/W
TPU5
TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCA5 Input capture at falling edge pin Input capture at both edges
0 output at compare match 1 output at compare match Toggle output at compare match
1
1
Legend: * : Don't care
TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCB5 Input capture at falling edge pin Input capture at both edges TGR5B Output disabled is output compare Initial output is 0 register output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care
Rev.4.00 Feb. 13, 2007 Page 711 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIER5--Timer Interrupt Enable Register 5
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FEA4
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU5
Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev.4.00 Feb. 13, 2007 Page 712 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSR5--Timer Status Register 5
Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FEA5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU5
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 713 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT5--Timer Counter 5
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FEA6
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU5
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR5A--Timer General Register 5A TGR5B--Timer General Register 5B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FEA8 H'FEAA
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU5 TPU5
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P1DDR--Port 1 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB0
3 0 W 2 0 W 1 0 W 0 0
Port 1
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : W
Specify input or output for individual port 1 pins
Rev.4.00 Feb. 13, 2007 Page 714 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
P2DDR--Port 2 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB1
3 0 W 2 0 W 1 0 W
Port 2
0 0 W
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write :
Specify input or output for individual port 2 pins
P3DDR--Port 3 Data Direction Register
Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 W 4 0 W
H'FEB2
3 0 W 2 0 W 1 0 W 0 0
Port 3
P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W
Undefined Undefined
Specify input or output for individual port 3 pins
P5DDR--Port 5 Data Direction Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- --
H'FEB4
3 0 W 2 0 W 1 0 W 0 0 W
Port 5
P53DDR P52DDR P51DDR P50DDR
Initial value : Undefined Undefined Undefined Undefined
Specify input or output for individual port 5 pins
Rev.4.00 Feb. 13, 2007 Page 715 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
P6DDR--Port 6 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB5
3 0 W 2 0 W 1 0 W 0 0
Port 6
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : Read/Write : W
Specify input or output for individual port 6 pins
PADDR--Port A Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB9
3 0 W 2 0 W 1 0 W
Port A
0 0 W
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Specify input or output for individual port A pins
PBDDR--Port B Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBA
3 0 W 2 0 W 1 0 W
Port B
0 0 W
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Specify input or output for individual port B pins
Rev.4.00 Feb. 13, 2007 Page 716 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PCDDR--Port C Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBB
3 0 W 2 0 W 1 0 W
Port C
0 0 W
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Specify input or output for individual port C pins
PDDDR--Port D Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBC
3 0 W 2 0 W 1 0 W
Port D
0 0 W
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write :
Specify input or output for individual port D pins
PEDDR--Port E Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBD
3 0 W 2 0 W 1 0 W 0 0
Port E
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : W
Specify input or output for individual port E pins
Rev.4.00 Feb. 13, 2007 Page 717 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PFDDR--Port F Data Direction Register
Bit : 7 6 5 4
H'FEBE
3 2 1
Port F
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4 to 6 Initial value Read/Write Modes 3, 7 Initial value Read/Write : : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Specify input or output for individual port F pins
PGDDR--Port G Data Direction Register
Bit Modes 1, 4, 5 Initial value Read/Write Initial value Read/Write : Undefined Undefined Undefined : -- -- -- 1 W 0 W : 7 -- 6 -- 5 -- 4
H'FEBF
3 2 1
Port G
0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Modes 2, 3, 6, 7 : Undefined Undefined Undefined : -- -- --
Specify input or output for individual port G pins
Rev.4.00 Feb. 13, 2007 Page 718 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK
-- -- -- -- -- -- -- -- -- -- --
Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K
: 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W
H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
3 -- 0 -- 2 IPR2 1 R/W
Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller
1 IPR1 1 R/W 0 IPR0 1 R/W
Bit
Initial value : Read/Write :
Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IRQ0 IRQ2 IRQ3 IPRC IRQ6 IRQ7 IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK WDT --* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 --* SCI channel 1 --* A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 IRQ1 IRQ4 IRQ5 DTC 2 to 0
Note: * Reserved bits. These bits cannot be modified and are always read as 1.
Rev.4.00 Feb. 13, 2007 Page 719 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
ABWCR--Bus Width Control Register
Bit : 7 ABW7 Modes 1 to 3, 5 to 7 Initial value : R/W Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4
H'FED0
3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1
Bus Controller
0 ABW0 1 R/W 0 R/W
ABW4
ABW1 1 R/W 0 R/W
Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access
Note: n = 7 to 0
ASTCR--Access State Control Register
Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W
H'FED1
3 AST3 1 R/W 2 AST2 1 R/W 1
Bus Controller
0 AST0 1 R/W
AST1 1 R/W
Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled Note: n = 7 to 0
Rev.4.00 Feb. 13, 2007 Page 720 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
WCRH--Wait Control Register H
Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3
H'FED2
2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W W51 1 R/W
Bus Controller
Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
Rev.4.00 Feb. 13, 2007 Page 721 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
WCRL--Wait Control Register L
Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3
H'FED3
2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W W11 1 R/W
Bus Controller
Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
Rev.4.00 Feb. 13, 2007 Page 722 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
BCRH--Bus Control Register H
Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W
H'FED4
3 0 R/W 2 -- 0 R/W 1 -- 0
Bus Controller
0 -- 0 R/W
BRSTRM BRSTS1 BRSTS0
R/W
Reserved Only 0 should be written to these bits Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access
Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states
Area 0 Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface
Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles
Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas
Rev.4.00 Feb. 13, 2007 Page 723 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
BCRL--Bus Control Register L
Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 EAE 1 R/W 4 -- 1 R/W
H'FED5
3 -- 1 R/W 2 -- 1 R/W 1 -- 0
Bus Controller
0 WAITE 0 R/W
R/W
Reserved Only 0 should be written to this bit WAIT Pin Enable 0 1 Wait input by WAIT pin disabled Wait input by WAIT pin enabled
Reserved Only 1 should be written to these bits External Addresses H'010000 to H'01FFFF Enable 0 1 On-chip ROM (H8S/2355) or reserved area* (H8S/2353) External addresses (in external expansion mode) or reserved area (in single-chip mode)
Note: * Do not access a reserved area. Reserved Only 0 should be written to this bit Bus Release Enable 0 1 External bus release is disabled External bus release is enabled
Rev.4.00 Feb. 13, 2007 Page 724 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
ISCRH -- IRQ Sense Control Register H ISCRL -- IRQ Sense Control Register L
ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0
H'FF2C H'FF2D
Interrupt Controller Interrupt Controller
11 0 R/W
10 0 R/W
9 0 R/W
8 0 R/W
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write : R/W
IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write :
IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Note: n = 7 to 0 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input
Rev.4.00 Feb. 13, 2007 Page 725 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
IER--IRQ Enable Register
Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4
H'FF2E
3 IRQ3E 0 R/W 2 IRQ2E 0 R/W
Interrupt Controller
1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IRQ4E 0 R/W
IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled
Note: n = 7 to 0
ISR--IRQ Status Register
Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4
H'FF2F
3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)*
Interrupt Controller
1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)*
IRQ4F 0 R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 726 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
DTCERA to DTCERF--DTC Enable Registers
Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W
H'FF30 to H'FF35
3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0
DTC
DTCE0 0 R/W
DTC Activation Enable
0 DTC activation by this interrupt is disabled [Clearing conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended
1
Correspondence between Interrupt Sources and DTCER
Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF 7 IRQ0 -- TGI2A -- -- RXI2 6 IRQ1 ADI TGI2B -- -- TXI2 5 IRQ2 TGI0A TGI3A TGI5A -- -- 4 IRQ3 TGI0B TGI3B TGI5B -- -- 3 IRQ4 TGI0C TGI3C CMIA0 RXI0 -- 2 IRQ5 TGI0D TGI3D CMIB0 TXI0 -- 1 IRQ6 TGI1A TGI4A CMIA1 RXI1 -- 0 IRQ7 TGI1B TGI4B CMIB1 TXI1 --
Rev.4.00 Feb. 13, 2007 Page 727 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
DTVECR--DTC Vector Register
Bit : 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W
H'FF37
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
DTC
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write :
Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended * During data transfer due to software activation
1
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
Rev.4.00 Feb. 13, 2007 Page 728 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SBYCR--Standby Control Register
Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W
H'FF38
3 OPE 1 R/W 2 -- 0 --
Power-Down State
1 -- 0 -- 0 -- 0 R/W
Reserved Only 0 should be written to this bit Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state
1
Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states
Rev.4.00 Feb. 13, 2007 Page 729 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SYSCR--System Control Register
Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4
H'FF39
3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0
MCU
INTM0 0 R/W
RAME 1 R/W
Reserved Only 0 should be written to this bit RAM Enable 0 1 On-chip RAM disabled On-chip RAM enabled
NMI Input Edge Select 0 1 Falling edge Rising edge
Interrupt Control Mode Selection 0 0 1 1 0 1 Reserved Only 0 should be written to this bit Interrupt control mode 0 -- Interrupt control mode 2 --
Rev.4.00 Feb. 13, 2007 Page 730 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCKCR--System Clock Control Register
Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 --
H'FF3A
3 -- 0 -- 2 SCK2 0 R/W
Clock Pulse Generator
1 SCK1 0 R/W 0 SCK0 0 R/W
Bus Master Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 Clock Output Control PSTOP 0 1 Normal Operation output Fixed high Sleep Mode output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance -- Bus master is in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 --
Rev.4.00 Feb. 13, 2007 Page 731 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
MDCR--Mode Control Register
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 --
H'FF3B
3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0
MCU
MDS0 --* R
Current mode pin operating mode Note: * Determined by pins MD2 to MD0
MSTPCRH -- Module Stop Control Register H MSTPCRL -- Module Stop Control Register L
MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1
H'FF3C H'FF3D
Power-Down State Power-Down State
MSTPCRL
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set
Reserved Register
Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 -- 0 R/W 4 -- 0 --
H'FF44
3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 --
Reserved Only 0 should be written to these bits
Rev.4.00 Feb. 13, 2007 Page 732 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PORT1--Port 1 Register
Bit : 7 P17 Initial value : Read/Write : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R
H'FF50
3 P13 --* R 2 P12 --* R 1 P11 --* R 0
Port 1
P10 --* R
State of port 1 pins Note: * Determined by the state of pins P17 to P10.
PORT2--Port 2 Register
Bit : 7 P27 Initial value : Read/Write : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R
H'FF51
3 P23 --* R 2 P22 --* R 1 P21 --* R 0
Port 2
P20 --* R
State of port 2 pins Note: * Determined by the state of pins P27 to P20.
PORT3--Port 3 Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 P35 --* R 4 P34 --* R
H'FF52
3 P33 --* R 2 P32 --* R 1 P31 --* R 0
Port 3
P30 --* R
Initial value : Undefined Undefined
State of port 3 pins Note: * Determined by the state of pins P35 to P30.
Rev.4.00 Feb. 13, 2007 Page 733 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PORT4--Port 4 Register
Bit : 7 P47 Initial value : Read/Write : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R
H'FF53
3 P43 --* R 2 P42 --* R 1 P41 --* R 0
Port 4
P40 --* R
State of port 4 pins Note: * Determined by the state of pins P47 to P40.
PORT5--Port 5 Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- --
H'FF54
3 P53 --* R 2 P52 --* R 1 P51 --* R 0
Port 5
P50 --* R
Initial value : Undefined Undefined Undefined Undefined
State of port 5 pins Note: * Determined by the state of pins P53 to P50.
PORT6--Port 6 Register
Bit : 7 P67 Initial value : Read/Write : --* R 6 P66 --* R 5 P65 --* R 4 P64 --* R
H'FF55
3 P63 --* R 2 P62 --* R 1 P61 --* R 0
Port 6
P60 --* R
State of port 6 pins Note: * Determined by the state of pins P67 to P60.
Rev.4.00 Feb. 13, 2007 Page 734 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PORTA--Port A Register
Bit : 7 PA7 Initial value : Read/Write : --* R 6 PA6 --* R 5 PA5 --* R 4 PA4 --* R
H'FF59
3 PA3 --* R 2 PA2 --* R 1 PA1 --* R
Port A
0 PA0 --* R
State of port A pins Note: * Determined by the state of pins PA7 to PA0.
PORTB--Port B Register
Bit : 7 PB7 Initial value : Read/Write : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R
H'FF5A
3 PB3 --* R 2 PB2 --* R 1 PB1 --* R
Port B
0 PB0 --* R
State of port B pins Note: * Determined by the state of pins PB7 to PB0.
PORTC--Port C Register
Bit : 7 PC7 Initial value : Read/Write : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R
H'FF5B
3 PC3 --* R 2 PC2 --* R 1 PC1 --* R
Port C
0 PC0 --* R
State of port C pins Note: * Determined by the state of pins PC7 to PC0.
Rev.4.00 Feb. 13, 2007 Page 735 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PORTD--Port D Register
Bit : 7 PD7 Initial value : Read/Write : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R
H'FF5C
3 PD3 --* R 2 PD2 --* R 1 PD1 --* R
Port D
0 PD0 --* R
State of port D pins Note: * Determined by the state of pins PD7 to PD0.
PORTE--Port E Register
Bit : 7 PE7 Initial value : Read/Write : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R
H'FF5D
3 PE3 --* R 2 PE2 --* R 1 PE1 --* R
Port E
0 PE0 --* R
State of port E pins Note: * Determined by the state of pins PE7 to PE0.
PORTF--Port F Register
Bit : 7 PF7 Initial value : Read/Write : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R
H'FF5E
3 PF3 --* R 2 PF2 --* R 1 PF1 --* R
Port F
0 PF0 --* R
State of port F pins Note: * Determined by the state of pins PF7 to PF0.
Rev.4.00 Feb. 13, 2007 Page 736 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PORTG--Port G Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 PG4 --* R
H'FF5F
3 PG3 --* R 2 PG2 --* R 1 PG1 --* R
Port G
0 PG0 --* R
Initial value : Undefined Undefined Undefined
State of port G pins Note: * Determined by the state of pins PG4 to PG0.
P1DR--Port 1 Data Register
Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4
H'FF60
3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0
Port 1
P14DR 0 R/W
P10DR 0 R/W
Stores output data for port 1 pins (P17 to P10)
P2DR--Port 2 Data Register
Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4
H'FF61
3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0
Port 2
P24DR 0 R/W
P20DR 0 R/W
Stores output data for port 2 pins (P27 to P20)
Rev.4.00 Feb. 13, 2007 Page 737 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
P3DR--Port 3 Data Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 P35DR 0 R/W 4
H'FF62
3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0
Port 3
P34DR 0 R/W
P30DR 0 R/W
Initial value : Undefined Undefined
Stores output data for port 3 pins (P35 to P30)
P5DR--Port 5 Data Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- --
H'FF64
3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0
Port 5
P50DR 0 R/W
Initial value : Undefined Undefined Undefined Undefined
Stores output data for port 5 pins (P53 to P50)
P6DR--Port 6 Data Register
Bit : 7 P67DR Initial value : Read/Write : 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4
H'FF65
3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0
Port 6
P64DR 0 R/W
P60DR 0 R/W
Stores output data for port 6 pins (P67 to P60)
Rev.4.00 Feb. 13, 2007 Page 738 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PADR--Port A Data Register
Bit : 7 PA7DR Initial value : Read/Write : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4
H'FF69
3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W
Port A
0 PA0DR 0 R/W
PA4DR 0 R/W
Stores output data for port A pins (PA7 to PA0)
PBDR--Port B Data Register
Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4
H'FF6A
3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W
Port B
0 PB0DR 0 R/W
PB4DR 0 R/W
Stores output data for port B pins (PB7 to PB0)
PCDR--Port C Data Register
Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4
H'FF6B
3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W
Port C
0 PC0DR 0 R/W
PC4DR 0 R/W
Stores output data for port C pins (PC7 to PC0)
Rev.4.00 Feb. 13, 2007 Page 739 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PDDR--Port D Data Register
Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4
H'FF6C
3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W
Port D
0 PD0DR 0 R/W
PD4DR 0 R/W
Stores output data for port D pins (PD7 to PD0)
PEDR--Port E Data Register
Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4
H'FF6D
3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W
Port E
0 PE0DR 0 R/W
PE4DR 0 R/W
Stores output data for port E pins (PE7 to PE0)
PFDR--Port F Data Register
Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4
H'FF6E
3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W
Port F
0 PF0DR 0 R/W
PF4DR 0 R/W
Stores output data for port F pins (PF7 to PF0)
Rev.4.00 Feb. 13, 2007 Page 740 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PGDR--Port G Data Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 0 R/W
H'FF6F
3 0 R/W 2 0 R/W 1 0 R/W
Port G
0 0 R/W
PG4DR PG3DR PG2DR
PG1DR PG0DR
Initial value : Undefined Undefined Undefined
Stores output data for port G pins (PG4 to PG0)
PAPCR--Port A MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF70
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port A
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Read/Write : R/W
Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis
PBPCR--Port B MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF71
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port B
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : R/W
Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis
Rev.4.00 Feb. 13, 2007 Page 741 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
PCPCR--Port C MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF72
3 0 R/W 2 0 R/W 1 0 R/W
Port C
0 0 R/W
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis
PDPCR--Port D MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF73
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port D
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : R/W
Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis
PEPCR--Port E MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF74
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port E
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : R/W
Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis
Rev.4.00 Feb. 13, 2007 Page 742 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
P3ODR--Port 3 Open Drain Control Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 0 R/W 4 0 R/W
H'FF76
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port 3
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR R/W
Initial value : Undefined Undefined
Controls the PMOS on/off status for each port 3 pin (P35 to P30)
PAODR--Port A Open Drain Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF77
3 0 R/W 2 0 R/W 1 0 R/W
Port A
0 0 R/W
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Read/Write :
Controls the PMOS on/off status for each port A pin (PA7 to PA0)
Rev.4.00 Feb. 13, 2007 Page 743 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SMR0--Serial Mode Register 0
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF78
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI0
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
Rev.4.00 Feb. 13, 2007 Page 744 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SMR0--Serial Mode Register 0
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF78
3 STOP 0 R/W 2 MP 0 R/W
Smart Card Interface 0
1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W
Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited
Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited
1
Note: etu: Elementary time unit (time for transfer of 1 bit)
Rev.4.00 Feb. 13, 2007 Page 745 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
BRR0--Bit Rate Register 0
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF79
3 1 R/W
SCI0, Smart Card Interface 0
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details.
Rev.4.00 Feb. 13, 2007 Page 746 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCR0--Serial Control Register 0
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF7A
1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W
SCI0
Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
1
0
1
Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev.4.00 Feb. 13, 2007 Page 747 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCR0--Serial Control Register 0
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF7A
1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W
Smart Card Interface 0
Initial value : Read/Write :
SCR setting
CKE0
SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1
SCK pin function
See SCI specification 0 1 0 1 0 1
Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev.4.00 Feb. 13, 2007 Page 748 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TDR0--Transmit Data Register 0
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF7B
3 1 R/W
SCI0, Smart Card Interface 0
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
Rev.4.00 Feb. 13, 2007 Page 749 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SSR0--Serial Status Register 0
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R
H'FF7C
1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
SCI0
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 750 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SSR0--Serial Status Register 0
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R
H'FF7C
1 MPB 0 R 0 MPBT 0 R/W
Smart Card Interface 0
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Note: etu: Elementary time unit (time for transfer of 1 bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status 0 [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 751 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
RDR0--Receive Data Register 0
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF7D
3 0 R
SCI0, Smart Card Interface 0
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR0--Smart Card Mode Register 0
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W
H'FF7E
2 SINV 0 R/W
SCI0, Smart Card Interface 0
1 -- 1 -- 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled
Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
Rev.4.00 Feb. 13, 2007 Page 752 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SMR1--Serial Mode Register 1
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF80
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI1
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
Rev.4.00 Feb. 13, 2007 Page 753 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SMR1--Serial Mode Register 1
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF80
3 STOP 0 R/W 2 MP 0 R/W
Smart Card Interface 1
1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W
Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited
Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited
1
Note: etu: Elementary time unit (time for transfer of 1 bit)
Rev.4.00 Feb. 13, 2007 Page 754 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
BRR1--Bit Rate Register 1
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF81
3 1 R/W
SCI1, Smart Card Interface 1
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details.
Rev.4.00 Feb. 13, 2007 Page 755 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCR1--Serial Control Register 1
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF82
1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W
SCI1
Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
1
0
1
Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev.4.00 Feb. 13, 2007 Page 756 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCR1--Serial Control Register 1
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF82
1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W
Smart Card Interface 1
Initial value : Read/Write :
SCR setting
CKE0
SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1
SCK pin function
See SCI specification 0 1 0 1 0 1
Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev.4.00 Feb. 13, 2007 Page 757 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TDR1--Transmit Data Register 1
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF83
3 1 R/W
SCI1, Smart Card Interface 1
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
Rev.4.00 Feb. 13, 2007 Page 758 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SSR1--Serial Status Register 1
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R
H'FF84
1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
SCI1
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 759 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SSR1--Serial Status Register 1
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R
H'FF84
1 MPB 0 R 0 MPBT 0 R/W
Smart Card Interface 1
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0
1
[Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1
1
Note: etu: Elementary time unit (time for transfer of 1 bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status 0 [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Overrun Error 0
1
[Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty
0
[Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 760 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
RDR1--Receive Data Register 1
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF85
3 0 R
SCI1, Smart Card Interface 1
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR1--Smart Card Mode Register 1
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3
H'FF86
2 SINV 0 R/W SDIR 0 R/W
SCI1, Smart Card Interface 1
1 -- 1 -- 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled
Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
Rev.4.00 Feb. 13, 2007 Page 761 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SMR2--Serial Mode Register 2
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF88
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI2
Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock
Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
Rev.4.00 Feb. 13, 2007 Page 762 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SMR2--Serial Mode Register 2
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF88
3 STOP 0 R/W 2 MP 0 R/W
Smart Card Interface 2
1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W
Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited
Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited
1
Note: etu: Elementary time unit (time for transfer of 1 bit)
Rev.4.00 Feb. 13, 2007 Page 763 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
BRR2--Bit Rate Register 2
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF89
3 1 R/W
SCI2, Smart Card Interface 2
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: See section 12.2.8, Bit Rate Register (BRR), for details.
Rev.4.00 Feb. 13, 2007 Page 764 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCR2--Serial Control Register 2
Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF8A
1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W
SCI2
Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
1
0
1
Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB = 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev.4.00 Feb. 13, 2007 Page 765 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SCR2--Serial Control Register 2
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF8A
1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W
Smart Card Interface 2
Initial value : Read/Write :
SCR setting
CKE0
SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1
SCK pin function
See SCI specification 0 1 0 1 0 1
Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled Reception enabled
Transmit Enable 0 1 Transmission disabled Transmission enabled
Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled
Rev.4.00 Feb. 13, 2007 Page 766 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TDR2--Transmit Data Register 2
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF8B
3 1 R/W
SCI2, Smart Card Interface 2
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
Rev.4.00 Feb. 13, 2007 Page 767 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SSR2--Serial Status Register 2
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R
H'FF8C
1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
SCI2
Multiprocessor Bit
0 1
[Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
Transmit End
0
[Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
1
Parity Error
0 1
[Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error
0 1
[Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0
Overrun Error
0 1
[Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0
[Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty
0
[Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 768 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
SSR2--Serial Status Register 2
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R
H'FF8C
1 MPB 0 R 0 MPBT 0 R/W
Smart Card Interface 2
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received
1
Note: etu: Elementary time unit (time for transfer of 1 bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status 0 [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] On of the next serial reception when RDRF= 1 completion
Receive Data Register Full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 769 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
RDR2--Receive Data Register 2
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF8D
3 0 R
SCI2, Smart Card Interface 2
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR2--Smart Card Mode Register 2
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W
H'FF8E
2 SINV 0 R/W
SCI2, Smart Card Interface 2
1 -- 1 -- 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled
Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
Rev.4.00 Feb. 13, 2007 Page 770 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
ADDRAH -- A/D Data Register AH ADDRAL -- A/D Data Register AL ADDRBH -- A/D Data Register BH ADDRBL -- A/D Data Register BL ADDRCH -- A/D Data Register CH ADDRCL -- A/D Data Register CL ADDRDH -- A/D Data Register DH ADDRDL -- A/D Data Register DL
Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0
H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97
7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R
A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter
2 -- 0 R 1 -- 0 R 0 -- 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : Read/Write : R
Stores the results of A/D conversion Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD
Rev.4.00 Feb. 13, 2007 Page 771 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
ADCSR--A/D Control/Status Register
Bit : 7 ADF Initial value : Read/Write : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W
H'FF98
3 CKS 0 R/W
Channel Select Group select CH2 0 Channel select CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1
A/D Converter
2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Single Mode Group Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7
Group Select 0 1 Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode Single mode Scan mode Conversion time = 266 states (max.) Conversion time = 134 states (max.)
A/D Interrupt Enable 0 A/D End Flag 0 1 A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled
[Clearing conditions] * When 0 is written to the ADF flag after reading ADF = 1 * When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When one round of conversion has been performed on all specified channels
1
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 772 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
ADCR--A/D Control Register
Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 --
H'FF99
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
A/D
Timer Trigger Select TRGS1 TRGS1 0 0 1 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled
DADR0--D/A Data Register 0 (Reserved in H8S/2393) DADR1--D/A Data Register 1 (Reserved in H8S/2393)
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFA4 H'FFA5
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
D/A D/A
Initial value : Read/Write :
Stores data for D/A conversion
Rev.4.00 Feb. 13, 2007 Page 773 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
DACR--D/A Control Register (Reserved in H8S/2393)
Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 --
H'FFA6
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
D/A
D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled
D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled
D/A Conversion Control DAOE1 DAOE0 0 0 1 DAE * 0 Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 Legend: * : Don't care * Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled
Rev.4.00 Feb. 13, 2007 Page 774 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR0--Time Control Register 0 TCR1--Time Control Register 1
Bit :
7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2
H'FFB0 H'FFB1
1 CKS1 0 R/W 0 CKS0 0 R/W CKS2 0 R/W
8-Bit Timer Channel 0 8-Bit Timer Channel 1
Initial value : Read/Write :
Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of /8 Internal clock: counted at falling edge of /64 Internal clock: counted at falling edge of /8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges
1 1 0 1
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input
Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled
Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled
Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled
Rev.4.00 Feb. 13, 2007 Page 775 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCSR0--Timer Control/Status Register 0 TCSR1--Timer Control/Status Register 1
TCSR0 Bit :
7 CMFB 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4
H'FFB2 H'FFB3
3 OS3 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 2 OS2 0 R/W ADTE 0 R/W 4 -- 1 --
8-Bit Timer Channel 0 8-Bit Timer Channel 1
1 OS1 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 0 OS0 0 R/W
Initial value : Read/Write : TCSR1 Bit :
Initial value : Read/Write :
Output Select 0 0 1 1 0 1 No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output)
Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output)
A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled
Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00)
Compare Match Flag A 0 [Clearing conditions] * Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA * When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORA
1
Compare Match Flag B 0 [Clearing conditions] * Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB * When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORB
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.4.00 Feb. 13, 2007 Page 776 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1
TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFB4 H'FFB5
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCORA1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1
TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFB6 H'FFB7
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCORB1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0--Timer Counter 0 TCNT1--Timer Counter 1
TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFB8 H'FFB9
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCNT1
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.4.00 Feb. 13, 2007 Page 777 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCSR--Timer Control/Status Register
Bit :
7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 --
H'FFBC (W) H'FFBC (R)
2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
WDT
Initial value : 0 Read/Write : R/(W)*
Clock Select CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Overflow period* (when = 20 MHz) 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s
/2 (initial value) 25.6 s /64 /128 /512 /2048 /8192 /32768 /131072
Timer Enable 0 1
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.
TCNT is initialized to H'00 and halted TCNT counts
Timer Mode Select 0 1 Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows
The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 778 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT--Timer Counter
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFBC (W) H'FFBD (R)
3 0 R/W 2 0 R/W 1 0 R/W 0 0
WDT
Initial value : Read/Write :
R/W
RSTCSR--Reset Control/Status Register
Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 --
H'FFBE (W) H'FFBF (R)
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
WDT
Reset Select 0 1 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Power-on reset Manual reset
Note: * The modules H8S/2355 Group are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation
Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access.
Rev.4.00 Feb. 13, 2007 Page 779 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSTR--Timer Start Register
Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W
H'FFC0
3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
TPU
Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.
TSYR--Timer Synchro Register
Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W
H'FFC1
3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
TPU
Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR.
Rev.4.00 Feb. 13, 2007 Page 780 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR0--Timer Control Register 0
Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FFD0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU0
CKEG1 CKEG0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1
Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 -- Count at rising edge Count at falling edge Count at both edges
Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Rev.4.00 Feb. 13, 2007 Page 781 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TMDR0--Timer Mode Register 0
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W
H'FFD1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU0
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend: * : Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation
TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation
Rev.4.00 Feb. 13, 2007 Page 782 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR0H--Timer I/O Control Register 0H
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFD2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU0
TGR0A I/O Control 0
0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock
0 output at compare match 1 output at compare match Toggle output at compare match
1
1
0
0
1 1 *
0 TGR0A is input 1 capture * register *
Legend: * : Don't care
TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * *
TGR0B Capture input is input source is compare TIOCB0 pin register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock
Legend: * : Don't care Note: *1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated.
Rev.4.00 Feb. 13, 2007 Page 783 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR0L--Timer I/O Control Register 0L
Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W
H'FFD3
1 IOC1 0 R/W 0 IOC0 0 R/W
TPU0
TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is input capture register Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock TGR0C Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
TGR0D I/O Control 0 0 0 0 TGR0D Output disabled is output 1 compare Initial output is 2 0 output 0 register* 1 1 0 0 1 1 0 1 1 0 0 0 TGR0D Capture input is input source is 1 capture TIOCD0 pin register*2 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges
0 output at compare match 1 output at compare match Toggle output at compare match
1
1 1 *
Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock
Legend: * : Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev.4.00 Feb. 13, 2007 Page 784 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIER0--Timer Interrupt Enable Register 0
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3
H'FFD4
2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
TPU0
TGIED 0 R/W
TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev.4.00 Feb. 13, 2007 Page 785 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSR0--Timer Status Register 0
Bit :
7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)*
H'FFD5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU0
Initial value : Read/Write :
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
1
Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 786 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT0--Timer Counter 0
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FFD6
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU0
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FFD8 H'FFDA H'FFDC H'FFDE
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU0 TPU0 TPU0 TPU0
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.4.00 Feb. 13, 2007 Page 787 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR1--Timer Control Register 1
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FFE0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 R/W
TPU1
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 1 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit in TSYR to 1.
Rev.4.00 Feb. 13, 2007 Page 788 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TMDR1--Timer Mode Register 1
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FFE1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU1
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend: * : Don't care Notes: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev.4.00 Feb. 13, 2007 Page 789 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR1--Timer I/O Control Register 1
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFE2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU1
TGR1A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is input capture register Capture input source is TIOCA1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture TGR1A Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care
TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0B compare match/input compare match/ capture input capture TGR1B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care
Rev.4.00 Feb. 13, 2007 Page 790 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIER1--Timer Interrupt Enable Register 1
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FFE4
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A
TPU1
0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev.4.00 Feb. 13, 2007 Page 791 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSR1--Timer Status Register 1
Bit :
7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FFE5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU1
Initial value : Read/Write :
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 792 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT1--Timer Counter 1
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFE6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU1
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FFE8 H'FFEA
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU1 TPU1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.4.00 Feb. 13, 2007 Page 793 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCR2--Timer Control Register 2
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FFF0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 R/W
TPU2
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024
Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 2 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1.
Rev.4.00 Feb. 13, 2007 Page 794 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TMDR2--Timer Mode Register 2
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FFF1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU2
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend: * : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
Rev.4.00 Feb. 13, 2007 Page 795 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIOR2--Timer I/O Control Register 2
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFF2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU2
TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match
1
1
Legend: * : Don't care
TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR2B is output compare register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match
Legend: * : Don't care
Rev.4.00 Feb. 13, 2007 Page 796 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TIER2--Timer Interrupt Enable Register 2
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FFF4
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU2
Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
Rev.4.00 Feb. 13, 2007 Page 797 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TSR2--Timer Status Register 2
Bit :
7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FFF5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU2
Initial value : Read/Write :
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
Rev.4.00 Feb. 13, 2007 Page 798 of 846 REJ09B0354-0400
Appendix B. Internal I/O Register
TCNT2--Timer Counter 2
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFF6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU2
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFF8 H'FFFA
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU2 TPU2
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.4.00 Feb. 13, 2007 Page 799 of 846 REJ09B0354-0400
Appendix C. I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1
P1n
RPOR1
Legend: WDDR1 : Write to P1nDDR WDR1 : Write to P1nDR RDR1 : Read P1nDR RPOR1 : Read port 1 Note: n = 0, 1, 4, and 6
Figure C.1 (a) Port 1 Block Diagram (Pins P10, P11, P14 and P16)
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Internal data bus
Input capture input
Appendix C. I/O Port Block Diagrams
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output
P1n
RDR1
RPOR1 Input capture input
External clock input
Legend: WDDR1 : Write to P1nDDR WDR1 : Write to P1nDR RDR1 : Read P1nDR RPOR1 : Read port 1 Note: n = 2, 3, 5, 7
Figure C.1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17)
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Internal data bus
Appendix C. I/O Port Block Diagrams
C.2
Port 2 Block Diagram
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output
P2n
RDR2
RPOR2 Input capture input Legend: WDDR2 : Write to P2nDDR WDR2 : Write to P2nDR RDR2 : Read P2nDR RPOR2 : Read port 2 Note: n = 0 or 1
Figure C.2 (a) Port 2 Block Diagram (Pins P20 and P21)
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Internal data bus
Appendix C. I/O Port Block Diagrams
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output
P2n
RDR2
RPOR2
Internal data bus
Input capture input 8-bit timer module Counter external reset input
Legend: WDDR2 : Write to P2nDDR WDR2 : Write to P2nDR RDR2 : Read P2nDR RPOR2 : Read port 2 Note: n = 2 or 4
Figure C.2 (b) Port 2 Block Diagram (Pins P22 and P24)
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Appendix C. I/O Port Block Diagrams
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 TPU module Output compare output/ PWM output enable Output compare output/ PWM output
P2n
RDR2
RPOR2
Internal data bus
Input capture input 8-bit timer module Counter external clock input Legend: WDDR2 : Write to P2nDDR WDR2 : Write to P2nDR RDR2 : Read P2nDR RPOR2 : Read port 2 Note: n = 3 or 5
Figure C.2 (c) Port 2 Block Diagram (Pins P23 and P25)
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Appendix C. I/O Port Block Diagrams
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2
P2n
RDR2
RPOR2
Legend: WDDR2 : Write to P2nDDR WDR2 : Write to P2nDR RDR2 : Read P2nDR RPOR2 : Read port 2 Note: n = 6 or 7
Figure C.2 (d) Port 2 Block Diagram (Pins P26 and P27)
Rev.4.00 Feb. 13, 2007 Page 805 of 846 REJ09B0354-0400
Internal data bus
8-bit timer Compare-match output enable Compare-match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output
Input capture input
Appendix C. I/O Port Block Diagrams
C.3
Port 3 Block Diagram
Reset R Q D P3nDDR C *1 WDDR3 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3
P3n
RPOR3
Legend: WDDR3 : Write to P3nDDR WDR3 : Write to P3nDR WODR3 : Write to P3nODR RDR3 : Read P3nDR RPOR3 : Read port 3 RODR3 : Read P3nODR Notes: 1. Output enable signal 2. Open drain control signal n = 0 or 1
Figure C.3 (a) Port 3 Block Diagram (Pins P30 and P31)
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Internal data bus
Appendix C. I/O Port Block Diagrams
Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3
RPOR3
Internal data bus
Serial receive data Legend: WDDR3 : Write to P3nDDR WDR3 : Write to P3nDR WODR3 : Write to P3nODR RDR3 : Read P3nDR RPOR3 : Read port 3 RODR3 : Read P3nODR Notes: 1. Output enable signal 2. Open drain control signal n = 2 or 3
Figure C.3 (b) Port 3 Block Diagram (Pins P32 and P33)
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Appendix C. I/O Port Block Diagrams
Reset R Q D P3nDDR C *2 WDDR3 Reset R Q D P3nDR C WDR3 *3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable
P3n *1
RPOR3
Legend: WDDR3 : Write to P3nDDR WDR3 : Write to P3nDR WODR3 : Write to P3nODR RDR3 : Read P3nDR RPOR3 : Read port 3 RODR3 : Read P3nODR Notes: 1. Priority order: Serial clock input > serial clock output > DR output 2. Output enable signal 3. Open drain control signal n = 4 or 5
Figure C.3 (c) Port 3 Block Diagram (Pins P34 and P35)
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Internal data bus Serial clock input
Appendix C. I/O Port Block Diagrams
C.4
Port 4 Block Diagram
Internal data bus
A/D converter module Analog input Legend: RPOR4 : Read port 4 Note: n = 0 to 5
RPOR4 P4n
Figure C.4 (a) Port 4 Block Diagram (Pins P40 to P45 in H8S/2355 and H8S/2353, Pins P40 to P47 in H8S/2393)
Internal data bus
A/D converter module Analog input D/A converter module Output enable Analog output
RPOR4 P4n
Legend: RPOR4 : Read port 4 Note: n = 6 or 7
Figure C.4 (b) Port 4 Block Diagram (Pins P46 and P47 in H8S/2355 and H8S/2353)
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Appendix C. I/O Port Block Diagrams
C.5
Port 5 Block Diagram
Reset R Q D P50DDR C WDDR5 Reset R Q D P50DR C WDR5 SCI module Serial transmit data output enable Serial transmit data RDR5
P50
RPOR5
Legend: WDDR5 WDR5 RDR5 RPOR5 : Write to P50DDR : Write to P50DR : Read P50DR : Read port 5
Figure C.5 (a) Port 5 Block Diagram (Pin P50)
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Internal data bus
Appendix C. I/O Port Block Diagrams
Reset R Q D P51DDR C WDDR5 Reset P51 R Q D P51DR C WDR5
RDR5
RPOR5
Legend: WDDR5 : Write to P51DDR WDR5 : Write to P51DR RDR5 : Read P51DR RPOR5 : Read port 5
Figure C.5 (b) Port 5 Block Diagram (Pin P51)
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Internal data bus
SCI module Serial receive data enable Serial receive data
Appendix C. I/O Port Block Diagrams
Reset R Q D P52DDR C WDDR5 Reset R Q D P52DR C WDR5
P52
RDR5
RPOR5
Legend: WDDR5 WDR5 RDR5 RPOR5 : Write to P52DDR : Write to P52DR : Read P52DR : Read port 5
Figure C.5 (c) Port 5 Block Diagram (Pin P52)
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Internal data bus
SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input
Appendix C. I/O Port Block Diagrams
Reset R Q D P53DDR C WDDR5 Reset P53 R Q D P53DR C WDR5
RDR5
RPOR5 A/D converter A/D converter external trigger input : Write to P53DDR : Write to P53DR : Read P53DR : Read port 5
Legend: WDDR5 WDR5 RDR5 RPOR5
Figure C.5 (d) Port 5 Block Diagram (Pin P53)
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Internal data bus
Appendix C. I/O Port Block Diagrams
C.6
Port 6 Block Diagram
Reset R Q D P6nDDR C WDDR6 Mode 1/2/3/7 P6n Mode 4/5/6 Reset R Q D P6nDR C WDR6
Internal data bus
Bus controller Chip select
RDR6
RPOR6
Legend: WDDR6 WDR6 RDR6 RPOR6 : Write to P6nDDR : Write to P6nDR : Read P6nDR : Read port 6
Note: n = 0 or 1
Figure C.6 (a) Port 6 Block Diagram (Pins P60 and P61)
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Appendix C. I/O Port Block Diagrams
Reset R Q D P6nDDR C WDDR6 Reset P6n R Q D P6nDR C WDR6 RDR6
RPOR6
Legend: WDDR6 : Write to P6nDDR WDR6 : Write to P6nDR RDR6 : Read P6nDR RPOR6 : Read port 6 Note: n = 2 or 3
Figure C.6 (b) Port 6 Block Diagram (Pins P62 and P63)
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Internal data bus
Appendix C. I/O Port Block Diagrams
Reset R Q D P6nDDR C WDDR6 Reset P6n R Q D P6nDR C WDR6 RDR6
RPOR6 Interrupt controller IRQ interrupt input Legend: WDDR6 : Write to P6nDDR WDR6 : Write to P6nDR RDR6 : Read P6nDR RPOR6 : Read port 6 Note: n = 4 or 5
Figure C.6 (c) Port 6 Block Diagram (Pins P64 and P65)
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Internal data bus
Appendix C. I/O Port Block Diagrams
Reset R Q D P6nDDR C WDDR6 Mode 1/2/3/7 P6n Mode 4/5/6 Reset R Q D P6nDR C WDR6
Internal data bus
Bus controller Chip select Interrupt controller IRQ interrupt input
RDR6
RPOR6
Legend: WDDR6 : Write to P6nDDR WDR6 : Write to P6nDR RDR6 : Read P6nDR RPOR6 : Read port 6 Note: n = 6 or 7
Figure C.6 (d) Port 6 Block Diagram (Pins P66 and P67)
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Appendix C. I/O Port Block Diagrams
C.7
Port A Block Diagram
Reset R Q D PAnPCR C WPCRA RPCRA
Internal data bus
Mode 4/5*3 Reset S R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA
PAn
Mode 1/2/3/6/7 Mode 4/5
RDRA
RPORA
Legend: WDDRA : Write to PAnDDR WDRA : Write to PAnDR WODRA : Write to PAnODR WPCRA : Write to PAnPCR RDRA : Read PAnDR RPORA : Read port A RODRA : Read PAnODR RPCRA : Read PAnPCR
Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority n = 0 to 3
Figure C.7 (a) Port A Block Diagram (Pins PA0 to PA3)
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Internal address bus
Appendix C. I/O Port Block Diagrams
Reset R Q D PA4PCR C WPCRA RPCRA
Internal data bus
Mode 4/5*3 Reset S R Q D PA4DDR C WDDRA *1 Reset R Q D PA4DR C WDRA *2 Reset R Q D PA4ODR C WODRA RODRA
PA4
Mode 1/2/3/6/7 Mode 4/5
RDRA
RPORA Interrupt controller Legend: WDDRA : Write to PA4DDR WDRA : Write to PA4DR WODRA : Write to PA4ODR WPCRA : Write to PA4PCR RDRA : Read PA4DR RPORA : Read port A RODRA : Read PA4ODR RPCRA : Read PA4PCR
IRQ interrupt input
Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority
Figure C.7 (b) Port A Block Diagram (Pin PA4)
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Internal address bus
Appendix C. I/O Port Block Diagrams
Reset R Q D PAnPCR C WPCRA RPCRA
Internal data bus
Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA
PAn
Mode 1/2/3/6/7 Mode 4/5
RDRA
RPORA Interrupt controller : Write to PAnDDR : Write to PAnDR : Write to PAnODR : Write to PAnPCR : Read PAnDR : Read port A : Read PAnODR : Read PAnPCR IRQ interrupt input
Legend: WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA
Notes: 1. Output enable signal 2. Open drain control signal n = 5 to 7
Figure C.7 (c) Port A Block Diagram (Pins PA5 to PA7)
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Internal address bus
Appendix C. I/O Port Block Diagrams
C.8
Port B Block Diagram
Reset R Q D PBnPCR C WPCRB RPCRB
Internal data bus
Mode 1/4/5* Reset S R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB
PBn
Mode 3/7 Mode 1/2/4/5/6
RDRB
RPORB
Legend: WDDRB WDRB WPCRB RDRB RPORB RPCRB : Write to PBnDDR : Write to PBnDR : Write to PBnPCR : Read PBnDR : Read port B : Read PBnPCR
Notes: * Set priority n = 0 to 7
Figure C.8 Port B Block Diagram (Pin PBn)
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Internal address bus
Appendix C. I/O Port Block Diagrams
C.9
Port C Block Diagram
Reset R Q D PCnPCR C WPCRC RPCRC
Mode 1/4/5* Reset S R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC
PCn
Mode 3/7 Mode 1/2/4/5/6
RDRC
RPORC
Legend: WDDRC : Write to PCnDDR WDRC : Write to PCnDR WPCRC : Write to PCnPCR RDRC : Read PCnDR RPORC : Read port C RPCRC : Read PCnPCR
Notes: * Set priority n = 0 to 7
Figure C.9 Port C Block Diagram (Pin PCn)
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Internal address bus
Internal data bus
Appendix C. I/O Port Block Diagrams
C.10
Port D Block Diagram
Reset
Internal upper data bus Internal lower data bus
R Q D PDnPCR C WPCRD RPCRD
Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD
External address write
PDn
Mode 3/7 Mode 1/2/4/5/6
External address upper write External address lower write
RDRD
RPORD
Legend: WDDRD : Write to PDnDDR WDRD : Write to PDnDR WPCRD : Write to PDnPCR RDRD : Read PDnDR RPORD : Read port D RPCRD : Read PDnPCR Note: n = 0 to 7
External address upper read
External address lower read
Figure C.10 Port D Block Diagram (Pin PDn)
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Appendix C. I/O Port Block Diagrams
C.11
Port E Block Diagram
Reset
Internal upper data bus Internal lower data bus
R Q D PEnPCR C WPCRE RPCRE
Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE
External address write
PEn
Mode 3/7 Mode 1/2/4/5/6
RDRE
RPORE
Legend: WDDRE : Write to PEnDDR WDRE : Write to PEnDR WPCRE : Write to PEnPCR RDRE : Read PEnDR RPORE : Read port E RPCRE : Read PEnPCR Note: n = 0 to 7
External address lower read
Figure C.11 Port E Block Diagram (Pin PEn)
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Appendix C. I/O Port Block Diagrams
C.12
Port F Block Diagram
Reset R Q D PF0DDR C
Mode 1/2/4/5/6
WDDRF Reset
PF0
R Q D PF0DR C WDRF
RDRF
RPORF
Internal data bus
Bus controller BRLE bit Bus request input
Legend: WDDRF : Write to PF0DDR WDRF : Write to PF0DR RDRF : Read PF0DR RPORF : Read port F
Figure C.12 (a) Port F Block Diagram (Pin PF0)
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Appendix C. I/O Port Block Diagrams
Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Mode 1/2/4/5/6
PF1
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF : Write to PF1DDR : Write to PF1DR : Read PF1DR : Read port F
Figure C.12 (b) Port F Block Diagram (Pin PF1)
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Internal data bus
Bus controller BRLE output Bus request acknowledge output
Appendix C. I/O Port Block Diagrams
Internal data bus
Reset R Q D PF2DDR C WDDRF Reset Mode 1/2/4/5/6 PF2 R Q D PF2DR C WDRF
Bus controller Wait enable
RDRF
RPORF
Wait input Legend: WDDRF : Write to PF2DDR WDRF : Write to PF2DR RDRF : Read PF2DR RPORF : Read port F
Figure C.12 (c) Port F Block Diagram (Pin PF2)
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Appendix C. I/O Port Block Diagrams
Reset R Q D PF3DDR C WDDRF Mode 3/7 PF3 Mode 1/2/4/5/6 Reset R Q D PF3DR C WDRF
Mode 1/2/4/5/6
Internal data bus
Bus controller LWR output RDRF
RPORF
Legend: WDDRF : Write to PF3DDR WDRF : Write to PF3DR RDRF : Read PF3DR RPORF : Read port F
Figure C.12 (d) Port F Block Diagram (Pin PF3)
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Appendix C. I/O Port Block Diagrams
Reset R Q D PF4DDR C WDDRF Mode 3/7 PF4 Mode 1/2/4/5/6 Reset R Q D PF4DR C WDRF
Mode 1/2/4/5/6
Internal data bus
Bus controller
HWR output
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF : Write to PF4DDR : Write to PF4DR : Read PF4DR : Read port F
Figure C.12 (e) Port F Block Diagram (Pin PF4)
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Appendix C. I/O Port Block Diagrams
Reset R Q D PF5DDR C WDDRF Mode 3/7 PF5 Mode 1/2/4/5/6 Reset R Q D PF5DR C WDRF
Mode 1/2/4/5/6
RDRF
RPORF
Legend: WDDRF WDRF RDRF RPORF : Write to PF5DDR : Write to PF5DR : Read PF5DR : Read port F
Figure C.12 (f) Port F Block Diagram (Pin PF5)
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Internal data bus
Bus controller RD output
Appendix C. I/O Port Block Diagrams
Reset R Q D PF6DDR C WDDRF Mode 3/7 PF6 Mode 1/2/4/5/6 Reset R Q D PF6DR C WDRF
Mode 1/2/4/5/6
RDRF
RPORF
Legend: WDDRF : Write to PF6DDR WDRF : Write to PF6DR RDRF : Read PF6DR RPORF : Read port F
Figure C.12 (g) Port F Block Diagram (Pin PF6)
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Internal data bus
Bus controller
AS output
Appendix C. I/O Port Block Diagrams
Mode 1/2/4/5/6* Reset S R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF
RDRF
RPORF
Legend: WDDRF : Write to PF7DDR WDRF : Write to PF7DR RDRF : Read PF7DR RPORF : Read port F Note: * Set priority
Figure C.12 (h) Port F Block Diagram (Pin PF7)
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Internal data bus
Appendix C. I/O Port Block Diagrams
C.13
Port G Block Diagram
Reset R Q D PG0DDR C WDDRG Reset PG0 R Q D PG0DR C WDRG
RDRG
RPORG
Legend: WDDRG : Write to PG0DDR WDRG : Write to PG0DR RDRG : Read PG0DR RPORG : Read port G
Figure C.13 (a) Port G Block Diagram (Pin PG0)
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Internal data bus
Appendix C. I/O Port Block Diagrams
Reset R Q D PGnDDR C WDDRG Mode 1/2/3/7 PGn Mode 4/5/6 Reset R Q D PGnDR C WDRG
Internal data bus Bus controller Chip select
RDRG
RPORG
Legend: WDDRG : Write to PGnDDR WDRG : Write to PGnDR RDRG : Read PGnDR RPORG : Read port G Note: n = 1 to 3
Figure C.13 (b) Port G Block Diagram (Pins PG1 to PG3)
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Appendix C. I/O Port Block Diagrams
Mode Mode 1/4/5 2/3/6/7 Reset
WDDRG Reset Mode 3/7 PG4 Mode 1/2/4/5/6 R Q D PG4DR C WDRG
RDRG
RPORG
Legend: WDDRG WDRG RDRG RPORG : Write to PG4DDR : Write to PG4DR : Read PG4DR : Read port G
Figure C.13 (c) Port G Block Diagram (Pin PG4)
Rev.4.00 Feb. 13, 2007 Page 835 of 846 REJ09B0354-0400
Internal data bus
S R Q D PG4DDR C
Bus controller Chip select
Appendix D. Pin States
Appendix D Pin States
D.1 Port States in Each Mode
Table D.1 I/O Port States in Each Processing State
MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 P47/DA1 1 to 7 1 to 7 1 to 7 1 to 7 PowerOn Reset T T T T Hardware Software Standby Standby Mode Mode T T T T kept kept kept [DAOE1 = 1] kept [DAOE1 = 0] T P46/DA0 1 to 7 T T T [DAOE0 = 1] kept [DAOE0 = 0] T P45 to P40 Port 5 P65 to P62 P67/CS7 P66/CS6 P61/CS5 P60/CS4 1 to 7 1 to 7 1 to 7 1 to 3, 7 4 to 6 T T T T T T kept kept kept kept T T T T T T kept kept kept T kept kept kept Input port I/O port I/O port I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 I/O port Address output kept I/O port Bus Release State kept kept kept kept Program Execution State Sleep Mode I/O port I/O port I/O port I/O port
Manual Reset kept kept kept T
[DDR * OPE = 0] T T [DDR * OPE = 1] H kept [OPE = 0] T [OPE = 1] kept kept T
Port A
1 to 3, 7 4, 5
T L
kept kept
T T
6
T
kept
T
[DDR * OPE = 0] T T [DDR * OPE = 1] kept
[DDR = 0] Input port [DDR = 1] Address output
Rev.4.00 Feb. 13, 2007 Page 836 of 846 REJ09B0354-0400
Appendix D. Pin States
Program Execution State Sleep Mode Address output
MCU Port Name Operating Pin Name Mode Port B 1, 4, 5
PowerOn Reset L
Manual Reset kept
Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] kept
Bus Release State T
2, 6
T
kept
T
[DDR * OPE = 0] T T [DDR * OPE = 1] kept kept [OPE = 0] T [OPE = 1] kept kept T
[DDR = 0] Input port [DDR = 1] Address output I/O port Address output
3, 7 Port C 1, 4, 5
T L
kept kept
T T
2, 6
T
kept
T
[DDR * OPE = 0] T T [DDR * OPE = 1] kept kept T kept kept T kept [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] H kept T kept kept T kept [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output
[DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output
3, 7 Port D 1, 2, 4 to 6 3, 7 Port E 1, 2, 8-bit 4 to 6 bus
T T T T
kept T* kept kept T* kept [DDR = 0] T [DDR = 1] Clock output kept
T T T T T T T
16-bit T bus 3, 7 PF7/ 1, 2, 4 to 6 T Clock output
3, 7
T
T
Rev.4.00 Feb. 13, 2007 Page 837 of 846 REJ09B0354-0400
Appendix D. Pin States
Program Execution State Sleep Mode AS, RD, HWR, LWR
MCU Port Name Operating Pin Name Mode PF6/AS PF5/RD PF4/HWR PF3/LWR 1, 2, 4 to 6
PowerOn Reset H
Manual Reset H*
Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] H kept [WAITE = 0] kept [WAITE = 1] T kept [BRLE = 0] kept [BRLE = 1] H kept [BRLE = 0] kept [BRLE = 1] T kept
Bus Release State T
3, 7 PF2/WAIT 1, 2, 4 to 6
T T
kept [WAITE = 0] kept [WAITE = 1] T kept [BRLE = 0] kept [BRLE = 1] BACK kept [BRLE = 0] kept [BRLE = 1] BREQ kept [DDR = 0] T [DDR = 1] H* kept kept [DDR = 0] T [DDR = 1] H*
T T
kept [WAITE = 0] kept [WAITE = 1] T kept L
I/O port [WAITE = 0] I/O port [WAITE = 1] WAIT I/O port [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ I/O port [DDR = 0] Input port [DDR = 1] CS0 I/O port I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3
3, 7 PF1/BACK 1, 2, 4 to 6
T T
T T
3, 7 PF0/BREQ 1, 2, 4 to 6
T T
T T
kept T
3, 7 PG4/CS0 1, 4, 5 2, 6
T H T
T T
kept
[DDR * OPE = 0] T T [DDR * OPE = 1] H kept kept kept kept
3, 7 PG3/CS1 PG2/CS2 PG1/CS3 1 to 3, 7 4 to 6
T T T
T T T
[DDR * OPE = 0] T T [DDR * OPE = 1] H
Rev.4.00 Feb. 13, 2007 Page 838 of 846 REJ09B0354-0400
Appendix D. Pin States
Program Execution State Sleep Mode I/O port I/O port
MCU Port Name Operating Pin Name Mode PG0 1 to 3, 7 4 to 6
PowerOn Reset T T
Manual Reset kept kept
Hardware Software Standby Standby Mode Mode T T kept kept
Bus Release State kept T
Legend: H L T kept DDR OPE WAITE BRLE Note: *
: High level : Low level : High impedance : Input port becomes high-impedance, output port retains state : Data direction register : Output port enable : Wait input enable : Bus release enable Indicates the state after completion of the executing bus cycle.
Rev.4.00 Feb. 13, 2007 Page 839 of 846 REJ09B0354-0400
Appendix E. Pin States at Power-On
Appendix E Pin States at Power-On
Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. After reset release, power-on reset exception handling is started. Note: * "Settle" refers to the pin states in a power-on reset in each MCU operating mode.
E.1
When Pins Settle from an Indeterminate State at Power-On
When the NMI pin level changes from low to high after powering on, the chip goes to the poweron reset state after a high level is detected at the NMI pin. While the chip detects a low level at the NMI pin, the manual reset state is established. The pin states are indeterminate during this interval. (Ports may output an internally determined value after powering on.) The NMI setup time (tNMIS) is necessary for the chip to detect a high level at the NMI pin.
VCC tOSC1
STBY Manual reset
Power-on reset
NMI RES
NMI = Low NMI = High RES = Low
Figure E.1 When Pins Settle from an Indeterminate State at Power-On
Rev.4.00 Feb. 13, 2007 Page 840 of 846 REJ09B0354-0400
Appendix E. Pin States at Power-On
E.2
When Pins Settle from the High-Impedance State at Power-On
When the STBY pin level changes from low to high after powering on, the chip goes to the poweron reset state after a high level is detected at the STBY pin. While the chip detects a low level at the STBY pin, it is in the hardware standby mode. During this interval, the pins are in the highimpedance state. After detecting a high level at the STBY pin, the chip starts oscillation.
VCC tOSC1
STBY Hardware standby mode
Power-on reset
NMI T1 RES Confirm t1min and tNMIS.
NMI = High RES = Low
Figure E.2 When Pins Settle from the High-Impedance State at Power-On
Rev.4.00 Feb. 13, 2007 Page 841 of 846 REJ09B0354-0400
Appendix F. Timing of Transition to and Recovery from Hardware Standby Mode
Appendix F Timing of Transition to and Recovery from Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
STBY t1 10tcyc RES t2 0ns
Figure F.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset.
STBY t 100ns RES tOSC tNMIRH
NMI
Figure F.2 Timing of Recovery from Hardware Standby Mode
Rev.4.00 Feb. 13, 2007 Page 842 of 846 REJ09B0354-0400
Appendix G. Product Lineup
Appendix G Product Lineup
Table G.1 H8S/2355 Group Product Lineup
Part No. HD6432355 HD6472355 HD6432353 HD6432393 Mark Code HD6432355(***)TE HD6432355(***)F ZTAT H8S/2353 H8S/2393 Mask ROM Mask ROM HD6472355TE HD6472355F HD6432353(***)TE HD6432353(***)F HD6432393(***)TE HD6432393(***)F Note: (***) is the ROM code. See table 1.1, for details. Package (Package Code) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 120-pin FP (FP-128)
Product Type H8S/2355 Mask ROM
Rev.4.00 Feb. 13, 2007 Page 843 of 846 REJ09B0354-0400
Appendix H. Package Dimensions
Appendix H Package Dimensions
Figures H.1 and H.2 show the TFP-120 and FP-128 package dimensions of the H8S/2355 Group.
JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g
HD
*1
D
90
61
91
60
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp b1
c1
*2
E
HE
c
Terminal cross section
ZE
Reference Dimension in Millimeters Symbol
120
31
A2
ZD
Index mark F
A
c
1
30
A1
L L1
Detail F
e
*3
y
bp
x
M
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Min Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.12 0.17 0.22 0.15 0.12 0.17 0.22 0.15 0 8 0.4 0.07 0.10 1.20 1.20 0.4 0.5 0.6 1.0
Figure H.1 TFP-120 Package Dimensions
Rev.4.00 Feb. 13, 2007 Page 844 of 846 REJ09B0354-0400
Appendix H. Package Dimensions
JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g
HD
*1
D 65 64
102 103
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
*2
HE
E
b1
c1
39
ZE
c
128 1 ZD Index mark 38
Terminal cross section
Reference Dimension in Millimeters Symbol
F
A1
L L1 e
*3
y
bp
x
M
Detail F
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom Max 20 14 2.70 21.8 22.0 22.2 15.8 16.0 16.2 3.15 0.00 0.10 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.10 0.10 0.75 0.75 0.3 0.5 0.7 1.0
Min
A
A2
Figure H.2 FP-128 Package Dimensions
Rev.4.00 Feb. 13, 2007 Page 845 of 846 REJ09B0354-0400
c
Appendix H. Package Dimensions
Rev.4.00 Feb. 13, 2007 Page 846 of 846 REJ09B0354-0400
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2355 Group
Publication Date: 1st Edition, April, 1997 Rev.4.00, February 13, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8S/2355 Group Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

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